Pulsed latch system with state retention and method of operation

An integrated circuit comprising:

• a pulse generator including:
• a logic gate circuit configured to operate on a non-continuous voltage source that does not supply power during power off modes;
• at least one delay circuit having an input that receives a clock signal and an output that provides a delayed clock signal, wherein a first input of the logic gate circuit is coupled to the clock signal and a second input of the logic gate circuit is coupled to the output of the at least one delay circuit, and an output of the logic gate circuit provides a delayed clock pulse which has a width proportional to a delay time provided by the at least one delay circuit;
• a pulse latch circuit including a clock input coupled to receive the delayed clock pulse, a data input coupled to receive a data value, and a data output, wherein the pulse latch circuit outputs and holds the data value at the data output each time the delayed clock pulse is provided at the clock input, and the pulse latch circuit operates on a continuous voltage source that supplies power during power on and power off modes.