Mix-mode PFC circuit and a method thereof

A control method of a PFC (Power Factor Correction) circuit, wherein the PFC circuit comprises a power circuit having at least one power switch, the control method comprising:

• producing an effective value of an input voltage of the PFC circuit;
• generating a compensation signal based on an output voltage of the PFC circuit and an output voltage reference signal;
• generating an on time signal based on the compensation signal, the effective value of the input voltage, a lower limit and an upper limit of the compensation signal;
• generating an on time delay signal based on the input voltage, the output voltage, the lower limit of the compensation signal, the effective value of the input voltage and the compensation signal;
• generating a current valley signal based on the input voltage, the effective value of the input voltage, the compensation signal, the upper limit of the compensation signal, and an inductance value of the inductor adopted by the PFC circuit;
• wherein
• the lower limit of the compensation signal represents a value of the compensation signal when the PFC circuit works at a transition time from critical current mode (CRM) to discontinuous current mode (DCM), and the upper limit of the compensation signal represents a value of the compensation signal when the PFC circuit works at a transition time from critical current mode (CRM) to continuous current mode (CCM).

A PFC circuit having at least a power switch, comprising:

• an analog-to-digital converting circuit, configured to receive an input voltage and an output voltage of the PFC circuit, and to provide a digitalized input voltage and a digitalized output voltage;
• a calculating circuit, configured to receive the digitalized input voltage and the digitalized output voltage, and to provide an on time signal, an on time delay signal and a valley current signal;
• a comparing circuit, configured to provide a comparing signal based on the valley current signal and an inductance current signal indicating a current flowing through an inductor of the PFC circuit;
• and
• a pulse circuit, configured to control on operation of the power switch based on the comparing signal and the on time delay signal, and to control off operation of the power switch based on the on time signal;
• wherein
• a minimum value of the on time signal is fixed to a first on time period value, and a maximum value of the on time signal is fixed to a second on time period value.