STT-MRAM heat sink and magnetic shield structure design for more robust read/write performance

A method comprising:

• patterning a film layer to form a film stack, the film stack having opposing side surfaces and a top surface extending between the opposing side surfaces;
• forming a first encapsulation layer directly on the opposing side surfaces and the top surface of the film stack;
• forming a heat sink layer over the first encapsulation layer;
• forming a second encapsulation layer over the heat sink layer;
• removing a portion of the second encapsulation layer and a portion of the heat sink layer disposed over top surface of the film stack to expose a portion of the first encapsulation layer that is disposed directly on the top surface of the film stack;
• removing the portion of the first encapsulation layer to expose the top surface of the film stack;
• after the removing of the portion of the first encapsulation layer to expose the top surface of the film stack, forming an interlayer dielectric layer on remaining portions of the first encapsulation layer, the heat sink layer and the second encapsulating layer;
• and
• forming a conductive line on the exposed top surface of the film stack, wherein the remaining portions of the first encapsulation layer, the heat sink layer and the second encapsulation layer all physically contact the interlayer dielectric layer after the forming of the conductive line.

A method of forming a magnetic thin film device, comprising:

• providing a thin film deposition;
• patterning said thin film deposition to produce a multiplicity of separate stacks;
• depositing a first encapsulation layer conformally over all exposed top and side surfaces of said stacks, said encapsulation layer being an oxidation prevention layer;
• forming a second encapsulation layer conformally over said first encapsulation layer, said second encapsulation layer being a heat sink layer, wherein said heat sink layer is chosen to have a coefficient of thermal expansion that provides stress relief during device operation;
• forming a third encapsulation layer conformally over said second encapsulation layer, said third encapsulation layer being a hard mask layer for patterning said heat sink layer;
• removing an upper portion of said heat sink layer by using said hard mask layer to create a self-aligned etch process, said etch process leaving remaining side portions of said heat sink layer to surround said first encapsulation layer that still conformally covers said stacks filling all spaces within said patterned deposition using an interlayer dielectric;
• and
• creating a planar top surface of said encapsulated deposition by a CMP process that removes portions of said encapsulated patterned deposition including upper portions of said first encapsulation layer and said heat sink layer and exposing an electrically conducting portion of said deposition to which an electrical connection can be made;
• then
• forming a conducting BIT line over said planarized surface to electrically contact said exposed upper portions of all said depositions, wherein the first encapsulation layer, the heat sink layer and the hard mask layer all physically contact the interlayer dielectric after the forming of the conducting BIT line.