Solar cell and method for manufacturing same

A method for manufacturing a solar cell, the solar cell including an n-type semiconductor layer and a p-type semiconductor layer on a first surface of a crystalline silicon substrate, the method comprising:

• a pattern layer forming step of forming a p-type semiconductor layer-formed region and a p-type semiconductor layer-non-formed region on the first surface of the crystalline silicon substrate, wherein the p-type semiconductor layer-formed region includes the p-type semiconductor layer and a protecting layer in this order on the first surface of the crystalline silicon substrate, and the p-type semiconductor layer-non-formed region includes neither the p-type semiconductor layer nor the protecting layer on the first surface of the crystalline silicon substrate;
• an n-type semiconductor layer forming step of forming the n-type semiconductor layer so as to cover an entire surface of both the p-type semiconductor layer-formed region and the p-type semiconductor layer-non-formed-region;
• an n-type semiconductor layer patterning step partially removing the n-type semiconductor layer on the p-type semiconductor layer-formed region so that a part of the protecting layer beneath the removed n-type semiconductor layer is exposed between the n-type semiconductor layers;
• and
• a protecting layer patterning step of removing the exposed protecting layer between the n-type semiconductor layers so that a part of the p-type semiconductor layer beneath the removed protecting layer is exposed between the n-type semiconductor layers,
• wherein
• the protecting layer includes:
• an underlying protecting layer that is in contact with the p-type semiconductor layer, and an insulating layer arranged on top of the underlying protecting layer so that the p-type semiconductor layer, the underlying protecting layer and the insulating layer are arranged in this order, and
• the underlying protecting layer including at least one selected from the group consisting of an intrinsic silicon-based layer and an n-type silicon-based layer,
• wherein in the protecting layer patterning step,
• the insulating layer is removed using a first etchant,
• after removing the insulating layer, the underlying protecting layer is removed using a second etchant,
• the first etchant exhibits a higher etching rate for the insulating layer than that for the underlying protecting layer, and
• the second etchant exhibits a higher etching rate for the underlying protecting layer than for the p-type semiconductor layer.