Non-volatile memory and manufacturing method for the same

A manufacturing method for a non-volatile memory, comprising the following steps:

• providing a substrate, and forming a sacrificial layer on the substrate;
• forming at least one shallow trench isolation structure in the sacrificial layer and the substrate, wherein a lower portion of the shallow trench isolation structure defines a plurality of active regions in the substrate;
• removing the sacrificial layer to obtain a plurality of grooves located on the substrate and defined by an upper portion of the shallow trench isolation structure;
• forming a first gate dielectric layer and a first conductive layer in sequence from bottom to top in the grooves, and planarizing the first conductive layer until the first conductive layer is leveled with a top surface of the shallow trench isolation structure;
• performing anisotropic etching to the first conductive layer to form a first sharp portion and a second sharp portion, wherein the first sharp portion and the second sharp portion are attached to two opposite sidewalls of the shallow trench isolation structure respectively;
• removing a part of the shallow trench isolation structure so that tips of the first sharp portion and the second sharp portion are higher than the top surface of the shallow trench isolation structure;
• forming at least one control gate structure on the first conductive layer, wherein the control gate structure comprises a second gate dielectric layer and a second conductive layer in sequence from bottom to top;
• removing a part of the first conductive layer, wherein the remaining first conductive layer and the first gate dielectric layer under the remaining first conductive layer form a floating gate structure, the control gate structure covers a partial area of the floating gate structure, a corner formed by one side surface of the floating gate structure and a part of a top surface of the floating gate structure is not covered by the control gate structure, and the corner is connected between the first sharp portion and one end of the second sharp portion;
• forming at least one erasing gate structure on the substrate, wherein the erasing gate structure is located on a side, which is provided with the corner, of the floating gate structure and comprises a tunneling dielectric layer and an erasing gate conductive layer in sequence from bottom to top, the tunneling dielectric layer covering the first sharp portion, the second sharp portion and a tip part of the corner;
• and
• forming at least one word line structure on the substrate, wherein the word line structure is located on a side, which is away from the corner, of the floating gate structure and comprises a third gate dielectric layer and a word line conductive layer in sequence from bottom to top;
• wherein removal of a part of the first conductive layer to form the floating gate structure comprises the following steps:
• forming a patterned photoresist layer to cover the first conductive layer above a source region;
• removing a part of the first conductive layer which is not covered by the patterned photoresist layer and the control gate structure;
• removing the patterned photoresist layer;
• forming at least one first sidewall structure on each side of the first conductive layer, each side of the control gate structure, and each side of the protection dielectric layer;
• forming at least one second sidewall structure on an external side of the first sidewall structure, and removing a part of the first gate dielectric layer which is not covered by the first conductive layer, the first sidewall structure and the second sidewall structure;
• removing a part of the first conductive layer which is not covered by the control gate structure, the first sidewall structure and the second sidewall structure;
• injecting ions to the source region;
• and
• removing at least a part of the second sidewall structure to expose the tip of the corner, the tip of the first sharp portion, and the tip of the second sharp portion, and removing a part of the first gate dielectric layer which is not covered by the first conductive layer.