US 10,854,754 B2Granted

Semiconductor device

AssigneeSamsung Electronics Co., Ltd.

InventorsSung Soo Kim, Dong Hyun Roh, Koung Min Ryu, Sang Jin Hyun

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Abstract

A semiconductor device includes an active fin on a substrate, a device isolation film covering a lower portion of the active fin, a gate structure covering the active fin and the device isolation film, and a gate spacer on a side wall of the gate structure, wherein a side wall of the gate structure disposed on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate structure to a bottom of the gate structure, and an inner side wall of the gate spacer on the device isolation film is inclined at a uniform inclination from a point higher than a half of a height of the gate spacer to a bottom of the gate spacer while forming an acute angle with a bottom surface of the gate spacer.

Claims20

Dependent claims

A semiconductor device comprising:

a substrate including a first region, a second region and a third region;
a plurality of fins disposed on the substrate, and including a first fin and a second fin;
a plurality of isolation films disposed on the substrate, and including a first isolation film disposed between the first fin and the second fin;
and
a plurality of gate structures including a first gate structure on the first region of the substrate, a second gate structure on the second region of the substrate and a third gate structure on the third region of the substrate,
wherein each of the plurality of gate structures is disposed on the plurality of fins and the plurality of isolation films,
a width of an upper portion of the first gate structure is greater than a width of a lower portion of the first gate structure,
a width of an upper portion of the second gate structure is substantially the same as a width of a lower portion of the second gate structure, and
a width of an upper portion of the third gate structure is less than a width of a lower portion of the third gate structure.

6 more elements

A semiconductor device comprising:

a substrate including a first region, a second region and a third region;
a plurality of fins disposed on the substrate, and including a first fin and a second fin;
a plurality of isolation films disposed on the substrate, and including a first isolation film disposed between the first fin and the second fin;
a plurality of gate structures including a first gate structure on the first region of the substrate, a second gate structure on the second region of the substrate and a third gate structure on the third region of the substrate;
a first gate spacer disposed on a sidewall of the first gate structure;
a second gate spacer disposed on a sidewall of the second gate structure;
and
a third gate spacer disposed on a sidewall of the third gate structure,
wherein each of the plurality of gate structures is disposed on the plurality of fins and the plurality of isolation films,
a ratio of a width of an upper portion of the first gate structure to a width of a lower portion of the first gate structure is different from a ratio of a width of an upper portion of the second gate structure to a width of a lower portion of the second gate structure,
the ratio of the width of the upper portion of the first gate structure to the width of the lower portion of the first gate structure is different from a ratio of a width of an upper portion of the third gate structure to a width of a lower portion of the third gate structure,
the ratio of the width of the upper portion of the second gate structure to the width of the lower portion of the second gate structure is different from the ratio of the width of the upper portion of the third gate structure to the width of the lower portion of the third gate structure,
a width of an upper portion of the first gate spacer is less than a width of a lower portion of the first gate spacer, and
a width of an upper portion of the third gate spacer is greater than a width of a lower portion of the third gate spacer.

11 more elements

A semiconductor device comprising:

a substrate including a first region, a second region and a third region;
a plurality of fins disposed on the substrate, and including a first fin and a second fin;
a plurality of isolation films disposed on the substrate, and including a first isolation film disposed between the first fin and the second fin;
a plurality of gate structures including a first gate structure on the first region of the substrate, a second gate structure on the second region of the substrate and a third gate structure on the third region of the substrate;
a first gate spacer disposed on a sidewall of the first gate structure;
a second gate spacer disposed on a sidewall of the second gate structure;
and
a third gate spacer disposed on a sidewall of the third gate structure,
wherein each of the plurality of gate structures is disposed on the plurality of fins and the plurality of isolation films,
a width of an upper portion of the first gate structure is greater than a width of a lower portion of the first gate structure,
a width of an upper portion of the third gate structure is less than a width of a lower portion of the third gate structure,
a width of an upper portion of the first gate spacer is less than a width of a lower portion of the first gate spacer, and
a width of an upper portion of the third gate spacer is greater than a width of a lower portion of the third gate spacer.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/932,076Filed 17 Jul 2020 · continuation
Priority: KR 10-2017-00276983 Mar 2017
Published: US 2020/0350429 A15 Nov 2020
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/6219
Fin field-effect transistors [FinFET]: characterised by the source or drain electrodes
H10D 64/017
Manufacture or treatment: using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e.…

Family

Application15/697,678Parent of this continuation · filed 7 Sep 2017
Application16/426,819Parent of this continuation · filed 30 May 2019
US 10,347,763 B2Parent of this continuation · filed 9 Jul 2019
US 2020/0350429 A1Pre-grant publication · published 5 Nov 2020
US 10,727,349 B2Parent of this continuation
US 2018/0254338 A1Published application
US 2019/0280116 A1Published application
US 10,854,754 B2This patent

From the US filing history. Foreign family members aren’t listed.