US 10,854,751 B2Granted

Semiconductor device having curved gate electrode aligned with curved side-wall insulating film and stress-introducing layer between channel region and source and drain regions

AssigneeSony Corporation

InventorsSatoru Mayuzumi, Hitoshi Wakabayashi

Life of this patent

Estimating the term…

Loading patent…

Abstract

A semiconductor device including a channel region formed in a semiconductor substrate; a source region formed on one side of the channel region; a drain region formed on the other side of the channel region; a gate electrode formed on the channel region with a gate insulating film therebetween; and a stress-introducing layer that applies stress to the channel region, the semiconductor device having a stress distribution in which source region-side and drain region-side peaks are positioned between a pn junction boundary of the channel region and the source region and a pn junction boundary of the channel region and the drain region.

Claims20

Dependent claims

A semiconductor device comprising:

a semiconductor substrate with a surface;
a channel region in the semiconductor substrate;
a gate electrode over the channel region and the surface of the semiconductor substrate;
a gate insulating film between the gate electrode and the channel region;
recesses in the surface on opposite sides of the gate electrode;
a first stress-introducing layer in the recesses to apply stress to the channel region,
a source region in the first stress-introducing layer at a source side of the channel region and a drain region in the first stress-introducing layer at a drain side of the channel region;
in a cross section, sidewalls flanking the gate electrode;
in the cross section, a source extension region extending from the source region to under the gate electrode and partially residing on the first stress-introducing layer, and a drain extension region extending from the drain region to under the gate electrode and partially residing on the first stress-introducing layer;
a second stress-introducing layer over the source region and the drain region, the second stress-introducing layer being a film with upper and lower surfaces that conform to outer surfaces of the sidewalls and a surface above the source and drain regions;
and
an interlayer insulating layer over the second stress-introducing layer,
wherein,
a width of a bottom portion of the gate electrode proximate to the semiconductor substrate is smaller than a width of an upper portion of the gate electrode distal to the semiconductor substrate,
in the cross section, the source extension region and the drain extension region extend to underneath the bottom portion of the gate electrode,
in the cross section, peaks of a stress distribution of a stress applied to the channel region by the first stress-introducing layer and the second stress-introducing layer are between ends of the gate electrode in a gate length direction.

13 more elements

A semiconductor device comprising:

a semiconductor substrate with a surface;
a channel region in the semiconductor substrate;
a gate electrode over the channel region and the surface of the semiconductor substrate;
a gate insulating film between the gate electrode and the channel region;
recesses in the surface on opposite sides of the gate electrode;
a first stress-introducing layer in the recesses to apply stress to the channel region,
a source region in the first stress-introducing layer at a source side of the channel region and a drain region in the first stress-introducing layer at a drain side of the channel region;
in a cross section, a source extension region extending from the source region to under the gate electrode and partially residing on the first stress-introducing layer, and a drain extension region extending from the drain region to under the gate electrode and partially residing on the first stress-introducing layer;
a second stress-introducing layer over the source region and the drain region;
a first side-wall insulating film within which is embedded the gate electrode;
a second side-wall insulating film between the second stress-introducing layer and the gate electrode;
and
a third side-wall insulating film between the second stress-introducing layer and the second side-wall insulating film,
wherein,
in the cross section, peaks of a stress distribution of a stress applied to the channel region by the first stress-introducing layer and the second stress-introducing layer are between ends of the gate electrode in a gate length direction,
the gate electrode includes at least one metal material,
the gate electrode comprises at least one selected from the group consisting of TiSi, Ni, NiSi, Hf, HfSi, W, Ta, TaSi, TaSiN, Co, CoSi, Ru, and Ir
the second stress-introducing layer is formed at opposite sides of the gate electrode without contacting the gate electrode, and not formed on the gate electrode,
the gate insulating film comprises at least one selected from the group consisting of HfO, HfAlO, HfSiO, TaO, and ZrO,
the first side-wall insulating film is between the second side-wall insulating film and the gate electrode,
each of the first side-wall insulating film and the second side-wall insulating film comprises SiO,
the third side-wall insulating film comprises SiN,
a thickness of the second side-wall insulating film is 2 nm to 10 nm,
a thickness of the first side-wall insulating film is 2 nm to 6 nm, and
the gate insulating film is between the gate electrode and the first side-wall insulating film, the gate insulating film having a curved shape aligned with the second side of the first side-wall insulating film.

22 more elements

A semiconductor device comprising:

a semiconductor substrate with a surface;
a channel region in the semiconductor substrate;
a gate electrode over the channel region and the surface of the semiconductor substrate;
a gate insulating film between the gate electrode and the channel region;
recesses in the surface on opposite sides of the gate electrode;
a first stress-introducing layer in the recesses to apply stress to the channel region,
a source region in the first stress-introducing layer at a source side of the channel region and a drain region in the first stress-introducing layer at a drain side of the channel region;
in a cross section, a source extension region extending from the source region to under the gate electrode and partially residing on the first stress-introducing layer, and a drain extension region extending from the drain region to under the gate electrode and partially residing on the first stress-introducing layer;
a second stress-introducing layer over the source region and the drain region;
a first side-wall insulating film within which is embedded the gate electrode;
a second side-wall insulating film between the second stress-introducing layer and the gate electrode;
and
a third side-wall insulating film between the second stress-introducing layer and the second side-wall insulating film,
wherein,
in the cross section, peaks of a stress distribution of a stress applied to the channel region by the first stress-introducing layer and the second stress-introducing layer are between ends of the gate electrode in a gate length direction,
the gate electrode includes at least one metal material,
the gate electrode comprises at least one selected from the group consisting of TiSi, Ni, NiSi, Hf, HfSi, W, Ta, TaSi, TaSiN, Co, CoSi, Ru, and Ir
the second stress-introducing layer is formed at opposite sides of the gate electrode without contacting the gate electrode, and not formed on the gate electrode,
the gate insulating film comprises at least one selected from the group consisting of HfO, HfAlO, HfSiO, TaO, and ZrO,
the first side-wall insulating film is between the second side-wall insulating film and the gate electrode,
each of the first side-wall insulating film and the second side-wall insulating film comprises SiO,
the third side-wall insulating film comprises SiN,
a thickness of the second side-wall insulating film is 2 nm to 10 nm,
a thickness of the first side-wall insulating film is 2 nm to 6 nm, and
the gate insulating film is between the gate electrode and the first side-wall insulating film, the gate insulating film having a curved shape aligned with the second side of the first side-wall insulating film.

22 more elements

A semiconductor device comprising:

a semiconductor substrate with a surface;
a channel region in the semiconductor substrate;
a gate electrode over the channel region and the surface of the semiconductor substrate;
a gate insulating film between the gate electrode and the channel region;
recesses in the surface on opposite sides of the gate electrode;
a first stress-introducing layer in the recesses to apply stress to the channel region,
a source region in the first stress-introducing layer at a source side of the channel region and a drain region in the first stress-introducing layer at a drain side of the channel region;
in a cross section, a source extension region extending from the source region to under the gate electrode and partially residing on the first stress-introducing layer, and a drain extension region extending from the drain region to under the gate electrode and partially residing on the first stress-introducing layer;
a second stress-introducing layer over the source region and the drain region;
a first side-wall insulating film within which is embedded the gate electrode;
a second side-wall insulating film between the second stress-introducing layer and the gate electrode;
and
a third side-wall insulating film between the second stress-introducing layer and the second side-wall insulating film,
wherein,
in the cross section, peaks of a stress distribution of a stress applied to the channel region by the first stress-introducing layer and the second stress-introducing layer are between ends of the gate electrode in a gate length direction,
the gate electrode includes at least one metal material,
the gate electrode comprises at least one selected from the group consisting of TiSi, Ni, NiSi, Hf, HfSi, W, Ta, TaSi, TaSiN, Co, CoSi, Ru, and Ir
the second stress-introducing layer is formed at opposite sides of the gate electrode without contacting the gate electrode, and not formed on the gate electrode,
the gate insulating film comprises at least one selected from the group consisting of HfO, HfAlO, HfSiO, TaO, and ZrO,
the first side-wall insulating film is between the second side-wall insulating film and the gate electrode,
each of the first side-wall insulating film and the second side-wall insulating film comprises SiO,
the third side-wall insulating film comprises SiN,
a thickness of the second side-wall insulating film is 2 nm to 10 nm,
a thickness of the first side-wall insulating film is 2 nm to 6 nm, and
a width of a bottom portion of the gate electrode proximate to the semiconductor substrate is smaller than a width of an upper portion of the gate electrode.

22 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/706,176Filed 6 Dec 2019 · continuation
Priority: JP 2009-14093012 Jun 2009
Published: US 2020/0119194 A116 Apr 2020
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10D 30/797
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: being in source or drain regions, e.g. SiGe source or drain
H10D 30/0227
Having source and drain regions or source and drain extensions self-aligned to sides of the gate: having both lightly-doped source and drain…
H10D 30/601
Insulated-gate field-effect transistors [IGFET]: having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
H10D 30/792
Arrangements for exerting mechanical stress on the crystal lattice of the channel regions: comprising applied insulating layers, e.g. stress liners

Family

Application12/783,248Parent of this continuation · filed 19 May 2010
Application14/819,115Parent of this continuation · filed 5 Aug 2015
US 9,153,663 B2Parent of this continuation · filed 6 Oct 2015
Application15/091,146Parent of this continuation · filed 5 Apr 2016
US 9,337,305 B2Parent of this continuation · filed 10 May 2016
Application15/416,739Parent of this continuation · filed 26 Jan 2017
US 9,601,622 B2Parent of this continuation · filed 21 Mar 2017
Application15/907,936Parent of this continuation · filed 28 Feb 2018
US 9,947,790 B2Parent of this continuation · filed 17 Apr 2018
Application16/296,448Parent of this continuation · filed 8 Mar 2019
US 10,269,961 B2Parent of this continuation · filed 23 Apr 2019
US 2020/0119194 A1Pre-grant publication · published 16 Apr 2020
US 10,535,769 B2Parent of this continuation
US 2010/0314694 A1Published application
US 2015/0340499 A1Published application
US 2016/0218213 A1Published application
US 2017/0148915 A1Published application
US 2018/0190820 A1Published application
US 2019/0207029 A1Published application
US 10,854,751 B2This patent

From the US filing history. Foreign family members aren’t listed.