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US 10,854,745 B2Granted
Memory device comprising an electrically floating body transistor and methods of using
AssigneeZeno Semiconductor, Inc.
InventorsJin-Woo Han, Dinesh Maheshwari, Yuniarto Widjaja
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Abstract
A semiconductor memory cell comprising an electrically floating body having two stable states is disclosed. A method of operating the memory cell is disclosed.
Claims20
A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells include:
- a memory transistor comprising a bi-stable floating body transistor having a first floating body region and a back-bias region configured to generate impact ionization when said memory cell is in one of first and second states, and wherein said back-bias region is configured so as not to generate impact ionization when the memory cell is in the other of said first and second states;
- and
- an access device;
- wherein said access device comprises a second floating body region;
- wherein said bi-stable floating body transistor and said access device are electrically connected in series;
- and
- wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.
5 more elements
A semiconductor memory array comprising:
- a plurality of semiconductor memory cells arranged in a matrix of rows and columns, wherein at least two of said semiconductor memory cells include:
- a first transistor having a first floating body;
- a second transistor having a second floating body;
- a buried layer underlying both of said first and second floating bodies;
- a first source line region contacting said first floating body;
- a first drain region separated from said first source line region and contacting said first floating body;
- a first gate insulated from said first floating body;
- an insulating member insulating said first floating body from said second floating body;
- a second source line region contacting said second floating body;
- a second drain region separated from said second source line region and contacting said second floating body;
- and
- a second gate insulated from said second floating body;
- wherein said first drain region is electrically connected to said second source line region;
- wherein a capacitance of said first floating body is different from a capacitance of said second floating body;
- and
- wherein said back-bias region is commonly connected to at least two of said semiconductor memory cells.
13 more elements
Dependencies are inferred from the claim text.