Method for producing IGBT with dV/dt controllability

A power semiconductor device, comprising:

• a first load terminal and a second load terminal, wherein the power semiconductor device is configured to conduct a load current along a vertical direction between the load terminals;
• a drift region of a first conductivity type;
• a plurality of IGBT cells, wherein each of the IGBT cells comprises a plurality of trenches that extend into the drift region along the vertical direction and that laterally confine at least one active mesa, the at least one active mesa comprising an upper section of the drift region;
• and
• an electrically floating barrier region of a second conductivity type that is spatially confined, in and against the vertical direction, by the drift region,
• wherein a total volume of all active mesas is divided into a first share and into a second share, the first share not laterally overlapping with the electrically floating barrier region and the second share laterally overlapping with the electrically floating barrier region,
• wherein the first share is configured to carry the load current at least within a range of 0% to 100% of a nominal load current for which the power semiconductor device is designed,
• wherein the second share is configured to carry the load current if the load current exceeds at least 0.5% of the nominal load current.