Dual metal gate structures for advanced integrated circuit structure fabrication

A method of fabricating an integrated circuit structure, the method comprising:

• forming a semiconductor substrate comprising an N well region having a first semiconductor fin protruding therefrom and a P well region having a second semiconductor fin protruding therefrom, the first semiconductor fin spaced apart from the second semiconductor fin, wherein the N well region is directly adjacent to the P well region in the semiconductor substrate;
• forming a trench isolation layer on the semiconductor substrate outside of and between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer;
• forming a gate dielectric layer on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins;
• forming a conductive layer over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen;
• forming a p type metal gate layer over the conductive layer over the first semiconductor fin but not over the second semiconductor fin, wherein a portion of the p type metal gate layer is over a portion of the gate dielectric layer on a portion of the trench isolation layer between the first semiconductor fin and the second semiconductor fin, and wherein the conductive layer is between and separates an entirety of the portion of the p type metal gate layer and the portion of the gate dielectric layer on the portion of the trench isolation layer between the first semiconductor fin and the second semiconductor fin;
• and
• forming an n type metal gate layer over the second semiconductor fin, wherein the n type metal gate layer is further over the trench isolation layer and over the p type metal gate layer.

A method of fabricating a computing device, the method comprising:

• providing a board;
• and
• coupling a component to the board, the component including an integrated circuit structure, comprising:
• a semiconductor substrate comprising an N well region having a first semiconductor fin protruding therefrom and a P well region having a second semiconductor fin protruding therefrom, the first semiconductor fin spaced apart from the second semiconductor fin, wherein the N well region is directly adjacent to the P well region in the semiconductor substrate;
• a trench isolation layer on the semiconductor substrate outside of and between the first and second semiconductor fins, wherein the first and second semiconductor fins extend above the trench isolation layer;
• a gate dielectric layer on the first and second semiconductor fins and on the trench isolation layer, wherein the gate dielectric layer is continuous between the first and second semiconductor fins;
• a conductive layer over the gate dielectric layer over the first semiconductor fin but not over the second semiconductor fin, the conductive layer comprising titanium, nitrogen and oxygen;
• a p type metal gate layer over the conductive layer over the first semiconductor fin but not over the second semiconductor fin, wherein a portion of the p type metal gate layer is over a portion of the gate dielectric layer on a portion of the trench isolation layer between the first semiconductor fin and the second semiconductor fin, and wherein the conductive layer is between and separates an entirety of the portion of the p type metal gate layer and the portion of the gate dielectric layer on the portion of the trench isolation layer between the first semiconductor fin and the second semiconductor fin;
• and
• an n type metal gate layer over the second semiconductor fin, wherein the n type metal gate layer is further over the trench isolation layer and over the p type metal gate layer.