Semiconductor device and method of forming vertical structure
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChih-Hao Wang, Wai-Yi Lien, Shi-Ning Ju, Kai-Chieh Yang, Wen-Ting Lan
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Abstract
According to an exemplary embodiment, a method of forming a vertical structure is provided. The method includes the following operations: providing a substrate; providing the vertical structure having a source, a channel, and a drain over the substrate; shrinking the source and the channel by oxidation; forming a metal layer over the drain of the vertical structure; and annealing the metal layer to form a silicide over the drain of the vertical structure.
Claims14
A method of manufacturing a semiconductor device, comprising:
- forming a first vertical structure including a semiconductor body portion and a hard mask portion disposed on the semiconductor body portion, the semiconductor body portion protruding from a semiconductor layer;
- forming an oxide layer on the semiconductor body portion and a surface of the semiconductor layer by oxidization;
- removing the oxide layer from the semiconductor body portion and the surface of the semiconductor layer, such that the semiconductor body portion and the surface of the semiconductor layer are exposed;
- after the oxide layer is removed, forming a gate dielectric layer around a part of the semiconductor body portion and forming a gate electrode layer over the gate dielectric layer;
- and
- after the gate dielectric layer and the gate electrode layer are formed, removing the hard mask portion by a chemical polishing process, wherein:
- after the oxide layer is removed, a width of the semiconductor body portion is smaller than a width of an upper portion of the hard mask portion,
- before the oxide layer is formed, the semiconductor body portion includes a source, a channel disposed over the source and a drain disposed over the channel,
- the method further comprises, after the hard mask portion is removed:
- forming a second dielectric layer;
- forming an etch stop layer over the second dielectric layer such that an upper portion of the drain is exposed and the etch stop layer is in contact with a top of the gate dielectric layer and a top of the gate electrode layer;
- and
- forming a drain silicide layer on the exposed drain, and
- after the drain silicide layer is formed, the drain covered by the drain silicide layer is narrow than the drain covered by the etch stop layer.
A method of manufacturing a semiconductor device, comprising:
- forming a first vertical structure including a semiconductor body portion and a hard mask portion disposed on the semiconductor body portion, the semiconductor body portion protruding from a semiconductor layer;
- forming an oxide layer on the semiconductor body portion and a surface of the semiconductor layer by oxidization;
- removing the oxide layer from the semiconductor body portion and the surface of the semiconductor layer, such that the semiconductor body portion and the surface of the semiconductor layer are exposed;
- after the oxide layer is removed, forming a gate dielectric layer around a part of the semiconductor body portion and forming a gate electrode layer over the gate dielectric layer;
- and
- after the gate dielectric layer and the gate electrode layer are formed, removing the hard mask portion by a chemical polishing process, wherein:
- after the oxide layer is removed, a width of the semiconductor body portion is smaller than a width of an upper portion of the hard mask portion,
- before the oxide layer is formed, the semiconductor body portion includes a source, a channel disposed over the source and a drain disposed over the channel,
- the method further comprises:
- forming an etch stop layer over the second dielectric layer such that an upper portion of the semiconductor body portion is exposed;
- and
- forming a first silicide layer on the exposed drain, and
- after the first silicide layer is formed, the exposed upper portion of the semiconductor body portion covered by the first silicide layer is narrow than the upper portion of the semiconductor body portion covered by the etch stop layer.
Dependencies are inferred from the claim text.