Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance

A method for making a FINFET comprising:

• forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween, the semiconductor fin being on a semiconductor layer, the source region comprising a source dopant diffusion blocking superlattice dividing the source region into a lower source region and an upper source region with the upper source region having a same conductivity and higher dopant concentration than the lower source region, the drain region comprising a drain dopant diffusion blocking superlattice dividing the drain region into a lower drain region and an upper drain region with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region;
• the upper drain region and upper source region each being raised above an upper surface of the semiconductor layer;
• each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
• and
• forming a gate on the channel region.

A method for making a FINFET comprising:

• forming spaced apart source and drain regions in a semiconductor fin with a channel region extending therebetween, the source region comprising a source dopant diffusion blocking superlattice dividing the source region into a lower source region and an upper source region with the upper source region having a same conductivity and higher dopant concentration than the lower source region, the drain region comprising a drain dopant diffusion blocking superlattice dividing the drain region into a lower drain region and an upper drain region with the upper drain region having a same conductivity and higher dopant concentration than the lower drain region;
• each of the source dopant diffusion blocking superlattice and drain dopant diffusion blocking superlattice comprising a respective plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions;
• forming a gate on the channel region;
• and
• forming a metal source contact on the upper source region, and a metal drain contact on the upper drain region;
• wherein the lower drain region comprises a different material than the upper drain region, and the lower source region comprises a different material than the upper source region;
• wherein the semiconductor fin is on a semiconductor layer and the upper source and drain regions are raised above an upper surface of the semiconductor layer.