Active matrix substrate, display device, and method for repairing defect of active matrix substrate

An active matrix substrate comprising:

• a substrate;
• multiple wiring lines that include multiple gate wiring lines and multiple source wiring lines, the multiple wiring lines being provided in the substrate;
• multiple thin film transistors each of which has a gate electrode, a source electrode, a drain electrode, and a first semiconductor layer, the multiple thin film transistors being supported on the substrate;
• multiple ESD protection circuits each of which is electrically connected to two wiring lines, among the multiple wiring lines;
• a gate metal layer that includes the multiple gate wiring lines and the gate electrodes of the multiple thin film transistors;
• and
• a source metal layer that includes the multiple source wiring lines and the source electrodes and the drain electrodes of the multiple thin film transistors,
• wherein each of the multiple EDS protection circuits includes at least one or more diode element,
• wherein each of the at least one or more diode elements includes
• a first electrode that is included in the gate metal layer,
• a second semiconductor layer that is formed on the same layer as the first semiconductor layer and at least partially overlaps the first electrode with an insulation layer in between, and
• a second electrode and a third electrode that are electrically connected to the second semiconductor layer, the second electrode and the third electrode being included in the source metal layer,
• wherein the first electrode and the second electrode of the at least one or more diode elements are electrically connected to each other,
• wherein each of the multiple ESD protection circuits further includes at least one or more reserve diode structures, and
• wherein each of the at least one or more reserve diode structures includes
• a fourth electrode that is in an electrically floating state, the fourth electrode being included in the gate metal layer, and
• a third semiconductor layer that is formed on the same layer as the first semiconductor layer and the second semiconductor layer and at least partially overlaps the fourth electrode with the insulation layer in between.