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US 10,854,637 B2Granted
Array substrate and display panel
AssigneeHkc Corporation Limited
InventorBeizhou Huang
Life of this patent
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Abstract
An array substrate and a display panel; the array substrate includes a substrate (6), a gate elelctrode (2), a gate insulation layer (1), a semiconductor active layer, a first etching barrier layer (4), and a source-drain layer (5); the gate elelctrode (2) is disposed at the substrate (6); and the gate insulation layer (1) covers the gate elelctrode (2).
Claims10
An array substrate, comprising:
- a substrate;
- a gate electrode, disposed at the substrate;
- a gate insulation layer, at least covering the gate electrode;
- a semiconductor active layer, disposed at a side of the gate insulation layer away from the gate electrode;
- a first etching barrier layer, disposed at a side of the semiconductor active layer away from the gate insulation layer, wherein two ends of the semiconductor active layer are exposed relative to the first etching barrier layer;
- and
- a source-drain layer, comprising a source electrode and a drain electrode respectively overlying on two ends of the first etching barrier layer and covering at least the two exposed ends of the semiconductor active layer relative to the first etching barrier layer, wherein the array substrate further comprises:
- a second etching barrier layer, disposed at the gate insulation layer and spaced apart from the first etching barrier layer and the semiconductor active layer, misaligned with the gate electrode.
5 more elements
An array substrate, comprising:
- a substrate;
- a gate electrode, disposed at the substrate;
- a gate insulation layer, at least covering the gate electrode;
- a semiconductor active layer, disposed at a side of the gate insulation layer away from the gate electrode, wherein the semiconductor active layer is an oxide semiconductor active layer;
- a first etching barrier layer, disposed at a side of the semiconductor active layer away from the gate insulation layer, wherein two ends of the semiconductor active layer are exposed relative to the first etching barrier layer;
- a second etching barrier layer, disposed at the gate insulation layer and spaced apart from the first etching barrier layer and the semiconductor active layer, misaligned with the gate electrode;
- and
- a source-drain layer, comprising a source electrode and a drain electrode respectively overlying two ends of the first etching barrier layer and covering at least the two exposed ends of the semiconductor active layer relative to the first etching barrier layer.
5 more elements
Dependencies are inferred from the claim text.