Three-dimensional vertical NOR flash thin-film transistor strings

A memory structure, comprising:

• a semiconductor substrate having a substantially planar surface and including circuitry formed therein for memory circuit operation;
• first, second and third thin-film NOR memory strings formed above the planar surface, each thin-film NOR memory string having a plurality of thin-film memory transistors, the thin-film memory transistors of each thin-film NOR memory string (i) sharing a common source region and a common drain region, each region extending lengthwise along a first direction substantially perpendicular to the planar surface, and (ii) having (a) one or more channel regions, each channel region being provided between and in contact with both the common drain region and the common source region, and (b) a plurality of gate electrodes that are spaced apart from each other and insulated from each other by a dielectric material, each gate electrode being positioned to be adjacent one of the channel regions, separated from its adjacent channel region by a charge-trapping material, each gate electrode extending lengthwise along a second direction substantially parallel the planar surface;
• first and second conductor segments, wherein the first conductor segment electrically connects both the common drain regions of the first and second thin-film NOR memory strings, and wherein the second conductor segment electrically connects the common drain region of the third thin-film NOR memory string;
• a third conductor segment electrically coupled to the circuitry in the semiconductor substrate;
• and
• first and second bit-line select transistors, wherein (i) the first bit-line select transistor, when biased to be conducting, connects the first conductor segment to the third conductor segment, and (ii) the second bit-line select transistor, when biased to be conducting, connects the second conductor segment to the third conductor segment.