Vertical memory devices and methods of manufacturing the same

A vertical memory device, comprising:

• first and second impurity regions sequentially stacked in a vertical direction substantially perpendicular to an upper surface of a substrate;
• a gate electrode structure including gate electrodes spaced apart from each other in the vertical direction on the second impurity region;
• a channel extending through the gate electrode structure, the second impurity region, and an upper portion of the first impurity region on the substrate in the vertical direction;
• a diffusion prevention pattern on the first impurity region, the diffusion prevention pattern configured to prevent impurities doped in the first impurity region from diffusing to neighboring layers;
• and
• a support pattern on the first impurity region,
• wherein the diffusion prevention pattern and the support pattern are in the second impurity region, and contact a sidewall of the second impurity region.

A vertical memory device, comprising:

• a gate electrode structure on a substrate, the gate electrode structure including gate electrodes spaced apart from each other in a vertical direction substantially perpendicular to an upper surface of the substrate;
• a channel extending through the gate electrode structure in the vertical direction on the substrate;
• a support pattern on the substrate, the support pattern being under the gate electrode structure;
• and
• a diffusion prevention pattern on the substrate, the diffusion prevention pattern contacting a bottom surface of the support pattern, a width of the diffusion prevention pattern in a horizontal direction substantially parallel to the upper surface of the substrate is less than a width of the support pattern in the horizontal direction, and a thickness of the diffusion prevention pattern in the vertical direction is less than a thickness of the support pattern in the vertical direction.