Semiconductor memory device having a channel structure vertically passing through a plurality of memory layers and having memory cell blocks and dummy memory cell blocks

A method of manufacturing a semiconductor memory device comprising:

• forming a first block and a second block on a substrate, the first block including a first cell array region and a first connection region, and the second block including a second cell array region and a second connection region;
• forming a stack structure of interlayer insulating layers and gate electrodes to extend from the first and second cell array regions to the first and second connection regions;
• forming a plurality of first cell channel structures in the first cell array region such that the first cell channel structures pass through the stack structure and are connected to the substrate via a plurality of first semiconductor structures;
• forming a plurality of first dummy channel structures in the first connection region such that the first dummy channel structures pass through the stack structure and are electrically isolated from the substrate;
• forming a plurality of second dummy channel structures in the second connection region such that the second dummy channel structures pass through the stack structure and are connected to the substrate via a plurality of second semiconductor structures;
• determining whether the first cell channel structures electrically connect the substrate by applying an electric charge to the second dummy channel structures and measuring current between the second dummy channel structures and the substrate;
• and
• providing a select one as the semiconductor memory device in response to the determining indicating that the first cell channel structures electrically connect the substrate.