Semiconductor device including vertical channel layer

A semiconductor device, comprising:

• a base layer on a substrate and having an n-type conductivity;
• a lower insulating layer on the base layer;
• a common source extension structure on the lower insulating layer and including a first semiconductor layer having an n-type conductivity;
• a plurality of channel structures on the common source extension structure and extending in a first direction perpendicular to an upper surface of the substrate, each of the plurality of channel structures having a first gate insulating layer and a channel layer;
• a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the plurality of channel structures in the first direction;
• and
• a common source region on the substrate, the common source region being in contact with a portion of a bottom surface of the common source extension structure and including a second semiconductor layer having an n-type conductivity,
• wherein the common source region has a first width measured in a second direction parallel to the upper surface of the substrate at an upper surface of the base layer, and the common source region has a second width greater than the first width measured in the second direction at an upper surface of the lower insulating layer.

A semiconductor device, comprising:

• a plurality of channel structures on a substrate, each channel structure of the plurality of channel structures extending in a first direction perpendicular to an upper surface of the substrate, and having a first gate insulating layer and a channel layer;
• a common source extension structure between the substrate and the plurality of channel structures, the common source extension structure including a first semiconductor layer and a second gate insulating layer, the first semiconductor layer having an n-type conductivity, the second gate insulating layer surrounding at least a portion of the first semiconductor layer;
• a plurality of gate electrodes on the common source extension structure and spaced apart from each other on a sidewall of each of the plurality of channel structures in the first direction;
• and
• a common source region on the substrate, the common source region being in contact with the common source extension structure and including a second semiconductor layer having an n-type conductivity,
• wherein the first semiconductor layer includes impurities at a first doping concentration, and the channel layer includes impurities at a second doping concentration different from the first doping concentration.