Three-dimensional memory device containing asymmetric, different size support pillars and method for making the same

A three-dimensional memory device comprising:

• an alternating stack of insulating layers and electrically conductive layers located over a substrate and comprising a staircase region having stepped surfaces;
• memory stack structures extending through the alternating stack, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film;
• first support pillar structures vertically extending through the staircase region of the alternating stack and having a first maximum lateral dimension;
• and
• second support pillar structures vertically extending through the staircase region of the alternating stack, having a second maximum lateral dimension that is different than the first maximum lateral dimension, and interlaced with the first support pillar structures;
• wherein:
• each of the memory films of the memory stack structures comprises a blocking dielectric layer, a charge storage layer, and a tunneling dielectric layer;
• each of the first support pillar structures comprises a respective first dielectric layer stack;
• each of the second support pillar structures comprises a respective second dielectric layer stack;
• each of the first dielectric layer stacks and the second dielectric layer stacks includes an outer dielectric layer having a same composition and a same thickness as the blocking dielectric layer, a middle dielectric layer having a same composition and a same thickness as the charge storage layer, and an inner dielectric layer having as same composition and a same thickness as the tunneling dielectric layer;
• each of the first support pillar structures comprises a first semiconductor channel material portion including a same material as the vertical semiconductor channels and laterally surrounded by a respective first dielectric layer stack;
• each of the second support pillar structures comprises a second semiconductor channel material portion including a same material as the vertical semiconductor channels and laterally surrounded by a respective second dielectric layer stack;
• each of the memory stack structures contacts a top surface of a respective pedestal channel portion;
• each of the first support pillar structures comprises a respective first pedestal semiconductor portion that contacts a bottom surface of a respective one of the first semiconductor channel material portions;
• and
• each of the second support pillar structures comprises a respective second semiconductor channel material portion that underlies, and is vertically spaced from, a respective one of the second semiconductor channel material portions.