US 10,854,623 B2Granted

Memory device

AssigneeSamsung Electronics Co., Ltd.

InventorsJang Hyun You, Jin Taek Park, Taek Soo Shin, Sung Yun Lee

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Abstract

A memory device including a substrate, a plurality of channel columns, a gate stack, an interlayer insulating layer, a plurality of first trenches, and at least one second trench. The substrate includes a cell array region and a connection region. The channel columns cross an upper surface of the substrate in the cell array region. The gate stack includes a plurality of gate electrode layers surrounding the channel columns in the cell array region. The gate electrode layers extend to different lengths in the connection region to form a stepped structure. The interlayer insulating layer is on the gate stack. The first trenches divide the gate stack and the interlayer insulating layer into a plurality of regions. The at least one second trench is inside of the interlayer insulating layer in the connection region and between the first trenches.

Claims20

Dependent claims

A memory device comprising:

a stack structure including mold insulating layers and gate electrode layers alternately stacked on a substrate, the stack structure extending from a cell array region of the substrate to a connection region of the substrate;
an interlayer insulating layer on the stack structure;
a plurality of channel columns penetrating through the stack structure in the cell array region;
a plurality of dummy columns penetrating through the stack structure in the connection region;
a plurality of contact plugs connected to the gate electrode layers in the connection region;
a plurality of trenches penetrating through the stack structure and the interlayer insulating layer, the plurality of trenches including a plurality of first trenches and at least two second trenches;
an isolation region penetrating through an upper gate electrode layer among the plurality of gate electrodes layers;
a first insulating layer in each of the plurality of first trenches;
and
a second insulating layer in each of the at least two second trenches,
wherein the plurality of first trenches extends from the cell array region to the connection region,
wherein the at least two second trenches are between the plurality of first trenches in the connection region,
wherein the first insulating layer is in contact with the upper gate electrode layer,
wherein an entirety of the second insulating layer is spaced apart from the upper gate electrode layer,
wherein the at least two second trenches include a first line portion and a second line portion,
wherein the first line portion and the second line portion extend in a first direction parallel to an upper surface of the substrate and are spaced apart from each other in a second direction perpendicular to the first direction, and
wherein an imaginary line extending from the isolation region in the first direction is between the first line portion and the second line portion, in a top view.

14 more elements

A memory device comprising:

a stack structure including a plurality of gate electrode layers extending from a cell array region of a substrate to a connection region of the substrate, the stack structure having a stepped structure in the connection region of the substrate;
an interlayer insulating layer on the stack structure;
a plurality of trenches penetrating through the stack structure and the interlayer insulating layer, the plurality of trenches including first trenches and at least two second trenches between the first trenches;
a first insulating layer in each of the first trenches;
and
a second insulating layer in each of the at least two second trenches,
wherein the first trenches extend from the cell array region to the connection region,
wherein the at least two second trenches are between the first trenches in the connection region,
wherein the first insulating layer is in contact with an upper gate electrode layer among the plurality of gate electrode layers, and
wherein an entirety of the second insulating layer is spaced apart from the upper gate electrode layer.

7 more elements

A memory device comprising:

a stack structure including a plurality of gate electrode layers extending from a cell array region of a substrate to a connection region of the substrate, the stack structure having a stepped structure in the connection region of the substrate;
an interlayer insulating layer on the stack structure;
a plurality of trenches penetrating through the stack structure and the interlayer insulating layer, the plurality of trenches including first trenches and at least two second trenches between the first trenches;
and
an isolation region,
wherein the first trenches extend from the cell array region to the connection region,
wherein the at least two second trenches include a first line portion and a second line portion in the connection region, the at least two second trenches being only in the connection region among the cell array region and the connection region of the substrate,
wherein the stack structure includes word lines and select lines on the word lines,
wherein the isolation region is between the select lines,
wherein the isolation region is on the word lines, and
wherein the first line portion and the second line portion of the at least two second trenches are spaced apart from the isolation region.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/509,708Filed 12 Jul 2019 · continuation
Priority: KR 10-2016-000596318 Jan 2016
Published: US 2019/0341396 A17 Nov 2019
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout

Family

Application15/295,119Parent of this continuation · filed 17 Oct 2016
US 2019/0341396 A1Pre-grant publication · published 7 Nov 2019
US 10,355,010 B2Parent of this continuation
US 2017/0207232 A1Published application
US 10,854,623 B2This patent

From the US filing history. Foreign family members aren’t listed.