Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsTakeo Mori, Takashi Terada
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device includes: first interconnect layers; second interconnect layers; a first memory pillar extending through the first interconnect layers; a second memory pillar extending through the second interconnect layers; a first film provided above the first interconnect layers, having a planar shape corresponding to the first interconnect layers and extending in the first direction; and a second film provided above the second interconnect layers, separate from the first film in the second direction, having a planar shape corresponding to the second interconnect layers and extending in the first direction. The first and second films have a compressive stress higher than a silicon oxide film.
Claims20
A semiconductor memory device comprising:
- a plurality of first interconnect layers extending in a first direction that is substantially parallel to a semiconductor substrate;
- a plurality of second interconnect layers extending in the first direction, and being separate from and adjacent to the first interconnect layers in a second direction that is substantially parallel to the semiconductor substrate and orthogonal to the first direction;
- a first memory pillar extending through the first interconnect layers in a third direction that is substantially vertical to the semiconductor substrate;
- a second memory pillar extending through the second interconnect layers in the third direction;
- a first film above the first interconnect layers, the first film having a planar shape corresponding to the first interconnect layers and extending in the first direction;
- a second film above the second interconnect layers, the second film being separate from the first film in the second direction, having a planar shape corresponding to the second interconnect layers and extending in the first direction;
- and
- a third film extending in the first direction between the first interconnect layers and the second interconnect layers, and having a compressive stress higher than a silicon oxide film,
- wherein the first and second films have a compressive stress higher than a silicon oxide film.
A semiconductor memory device comprising:
- a plurality of first interconnect layers extending in a first direction that is substantially parallel to a semiconductor substrate;
- a plurality of second interconnect layers extending in the first direction, and being separate from and adjacent to the first interconnect layers in a second direction that is substantially parallel to the semiconductor substrate and orthogonal to the first direction;
- a first memory pillar extending through the first interconnect layers in a third direction that is substantially vertical to the semiconductor substrate;
- a second memory pillar extending through the second interconnect layers in the third direction;
- a first film above the first interconnect layers, the first film having a planar shape corresponding to the first interconnect layers and extending in the first direction;
- a second film above the second interconnect layers, the second film being separate from the first film in the second direction, having a planar shape corresponding to the second interconnect layers and extending in the first direction;
- a first conductive layer between the first interconnect layers and the second interconnect layers and between the first film and the second film, the first conductive layer extending in the first direction and being electrically coupled to a diffusion layer formed in the semiconductor substrate;
- a first insulating layer between the first interconnect layers and the first conductive layer;
- and
- a second insulating layer between the second interconnect layers and the first conductive layer,
- wherein the first and second films have a compressive stress higher than a silicon oxide film.
Dependencies are inferred from the claim text.