Three-dimensional memory device containing bit line switches

A device, comprising:

• first memory stack structures extending through a first alternating stack of first insulating layers and first electrically conductive layers in a first memory block region;
• second memory stack structures extending through a second alternating stack of second insulating layers and second electrically conductive layers in a second memory block region, wherein each of the first and second memory stack structures comprises a respective vertical semiconductor channel and memory film;
• a first portion of a first bit line electrically connected to the first memory stack structures;
• a second portion of the first bit line electrically connected to the second memory stack structures;
• a first interconnect located between the first and the second memory block regions;
• and
• a sense amplifier, wherein the sense amplifier is electrically connected to the first and the second portions of the first bit line through the first interconnect.

A memory chip comprising:

• a first memory block region;
• a second memory block region;
• a first switch;
• a second switch;
• a first portion of a first bit line traversing the first memory block region and electrically connected to the first switch;
• a second portion of the first bit line traversing the second memory block region and electrically connected to the second switch;
• a first interconnect;
• a sense amplifier electrically connected to the first portion of the first bit line through the first switch, and the sense amplifier electrically connected to the second portion of the first bit line through the second switch;
• and
• a memory array controller;
• wherein:
• the sense amplifier is located below the first and the second memory block regions;
• and
• the first interconnect extends below the first and the second memory block regions to electrically contact the sense amplifier.