Memory device and method of forming the same

A memory device, comprising:

• a conductive reference layer, coupled to a reference voltage level, the conductive reference layer having an upper surface and a lower surface facing opposite to the upper surface;
• a first plurality of strings of transistors, each of the first plurality of strings having a first terminal coupled to the upper surface of the conductive reference layer, a second terminal coupled to a first bit line, and each of the first plurality of transistor strings controlled by a plurality of first word line signals, wherein each of the first plurality of strings of transistors includes a first channel layer disposed on the upper surface of the conductive layer and extending perpendicular to the conductive layer;
• a first dielectric layer, arranged to surround substantially an entire length of the first channel layer;
• a plurality of first conductive layers, disposed on and in parallel with the conductive reference layer;
• and a plurality of first insulating layers, alternately disposed on the plurality of first conductive layers, wherein the first channel layer is formed from a continuous solid conductive material in cross section;
• a second plurality of strings of transistors, each of the first plurality of strings having a first terminal coupled to the lower surface of the conductive reference layer, a second terminal coupled to a second bit line, and each of the second plurality of strings of transistors controlled by a plurality of second word line signals, wherein each of the second plurality of strings of transistors includes a second channel layer disposed on the lower surface of the conductive reference layer and extending perpendicular to the conductive reference layer, each of the second plurality of strings of transistors being aligned with a corresponding one of the first plurality of strings of transistors;
• a second dielectric layer, arranged to surround substantially an entire length of the second channel layer, wherein the second channel layer and the second dielectric layer are aligned to the first channel layer and the first dielectric layer respectively;
• a plurality of second conductive layers, disposed on and in parallel with the conductive reference layer;
• and a plurality of second insulating layers, alternately disposed on the plurality of second conductive layers, wherein the second channel layer is formed from a continuous solid conductive material in cross section;
• at least a first conductive via disposed on a second end of the first channel layer and operatively connected to at least a first bit line;
• at least a second conductive via disposed on a second end of the second channel layer and operatively connected to at least a second bit line;
• an interconnection layer, the second string of transistors being disposed on an upper surface of the interconnection layer;
• and
• a substrate layer, a lower surface of the interconnection layer being coupled an upper surface of the substrate layer, wherein the first string of transistors and the second string of transistors are operatively connected to the conductive reference layer such that a first current flowing through the first storage portion and a second current flowing through the second storage portion during operation flow into the conductive reference layer at the reference voltage level.

A memory device, comprising:

• a substrate;
• an interconnecting layer, disposed on the substrate;
• a conductive reference layer, coupled to a reference voltage level, and connected to the interconnecting layer;
• and
• a storage portion, disposed on the interconnecting layer, wherein the storage portion comprises:
• a plurality of first storage strings, vertically coupled to an upper surface of the conductive reference layer relative to a horizontal plane of the conductive reference layer, and
• a plurality of second storage strings, vertically coupled to a lower surface of the conductive reference layer relative to the horizontal plane of the conductive reference layer, wherein the lower surface is facing opposite to the upper surface, wherein the plurality of first storage strings and the plurality of second storage strings are operatively connected to the conductive reference layer such that a first current flowing through the plurality of first storage strings and a second current flowing through the plurality of second storage strings during operation flow into the conductive reference layer at the reference voltage level,
• wherein each of the plurality of second storage strings being aligned with a corresponding one of the plurality of first storage strings,
• wherein each of the plurality of first storage strings includes a first channel layer disposed on the upper surface of the conductive reference layer and extending perpendicular to the conductive reference layer;
• a first dielectric layer, arranged to surround substantially an entire length of the first channel layer;
• a plurality of first conductive layers;
• and a plurality of first insulating layers, interlaced with the plurality of first conductive layers, the first channel layer being formed from a continuous solid conductive material in cross section, and
• wherein each of the plurality of second storage strings includes a second channel layer disposed on the lower surface of the conductive reference layer and extending perpendicular to the conductive reference layer;
• a second dielectric layer, arranged to surround substantially an entire length of the second channel layer;
• a plurality of second conductive layers;
• and a plurality of second insulating layers, interlaced with the plurality of second conductive layers, the second channel layer being formed from a continuous solid conductive material in cross section.