Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors

An integrated assembly, comprising:

• a first transistor having a horizontally-extending channel region between a first source/drain region and a second source/drain region;
• a second transistor having a vertically-extending channel region between a third source/drain region and a fourth source/drain region;
• a capacitor having a first electrode, a second electrode, and an insulative material between the first and second electrodes;
• the first electrode being electrically connected with the first source/drain region and the second electrode being electrically connected with the third source/drain region, the first transistor, the second transistor and the capacitor all being comprised by a first memory device;
• a digit line electrically connected with the second source/drain region;
• and
• a conductive structure electrically connected with the fourth source/drain region;
• a second memory device is adjacent to the first memory device;
• the second memory device comprising a third transistor having a horizontally-extending channel region, a fourth transistor having a vertically-extending channel region, and a second capacitor between the third and fourth transistors;
• and
• the second source/drain region being shared between the first transistor and the third transistor, and wherein the conductive structure is not electrically coupled with the second memory device.

Integrated memory, comprising:

• ferroelectric memory devices within a memory array;
• the ferroelectric memory devices being in paired arrangements, with each paired arrangement comprising a first ferroelectric memory device and a second ferroelectric memory device;
• each of the first ferroelectric memory devices including a first transistor having a horizontally-extending first channel region, a second transistor having a vertically-extending second channel region, and a first capacitor between the first and second transistors;
• each of the second ferroelectric memory devices including a third transistor having a horizontally-extending third channel region, a fourth transistor having a vertically-extending fourth channel region, and a second capacitor between the third and fourth transistors;
• each of the first transistors having first and second source/drain region on opposing sides of its channel region;
• each of the second transistors having third and fourth source/drain regions on opposing sides of its channel region;
• each of the third transistors having a fifth source/drain region on one side of its channel region, and having the second source/drain region on an opposing side of its channel region;
• each of the fourth transistors having sixth and seventh source/drain regions on opposing sides of its channel region;
• the first and fifth source/drain regions being electrically coupled with the first and second capacitors, respectively;
• the third and sixth source/drain regions being electrically coupled with the first and second capacitors, respectively;
• the first, second, third and fourth transistors having first, second, third and fourth transistor gates, respectively, which are operatively adjacent to the first, second, third and fourth channel regions, respectively;
• digit lines electrically connected with the second source/drain regions, and extending along columns of the memory array;
• wordlines electrically connected with the first and third transistor gates, and extending along rows of the memory array;
• MUX lines electrically connected with the second and fourth transistor gates;
• and
• plate lines electrically connected with the fourth and seventh source/drain regions.