Semiconductor structure and method forming the same

A semiconductor structure, comprising:

• a stacked structure including a plurality of stacked layers on a substrate having an array area and a staircase area, wherein each of the stacked layer has a pair of a dielectric layer and a conductive layer under the dielectric layer, and the stacked structure has a staircase structure on the staircase area;
• a plurality of slits disposed in the stacked structure to expose the substrate, wherein the slits have a first width in the array area and have a second width in the staircase area, and the first width is narrower than the second width;
• and
• a plurality of reference marks disposed along at least one side of the slits in the staircase structure, wherein the plurality of reference marks overlap the staircase structure.

A method of forming a semiconductor structure, comprising:

• forming a stacked structure including a plurality of stacked layers on a substrate having an array area and a staircase area, wherein each of the stacked layer has a pair of a dielectric layer and a sacrificial layer under the dielectric layer;
• forming reference marks by etching a topmost one of the stacked layers respectively at target positions along slit areas predetermined for forming slits;
• performing a first etch-trim cycle, which comprises:
• forming a first photoresist pattern on the substrate to expose an outermost reference mark;
• etching the topmost one of the stacked layers exposed by the first photoresist pattern;
• trimming the first photoresist pattern to retreat the boundary of the first photoresist pattern back for a predetermined distance or expose the reference mark next to the previously exposed reference mark;
• repeating the etching step and the trimming step for several times;
• and
• removing the first remained part of the first photoresist pattern;
• and
• forming slits by etching the stacked structure on the slit areas until the substrate is exposed.