US 10,854,615 B2Granted

FinFET having non-merging epitaxially grown source/drains

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsChun Po Chang, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Wei-Yang Lee, Tzu-Hsiang Hsu

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Abstract

A semiconductor device includes a layer having a semiconductive material. The layer includes an outwardly-protruding fin structure. An isolation structure is disposed over the layer but not over the fin structure. A first spacer and a second spacer are each disposed over the isolation structure and on sidewalls of the fin structure. The first spacer is disposed on a first sidewall of the fin structure. The second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall. The second spacer is substantially taller than the first spacer. An epi-layer is grown on the fin structure. The epi-layer protrudes laterally. A lateral protrusion of the epi-layer is asymmetrical with respect to the first side and the second side.

Claims20

Dependent claims

A semiconductor device, comprising:

a layer that includes a semiconductive material, the layer including an outwardly-protruding fin structure;
a first isolation structure disposed over the layer;
a first spacer and a second spacer each disposed over the first isolation structure, wherein the first spacer is disposed on a first sidewall of the fin structure, wherein the second spacer is disposed on a second sidewall of the fin structure opposite the first sidewall, and wherein the second spacer is taller than the first spacer;
an epi-layer grown on the fin structure, wherein the epi-layer has a lateral protrusion disposed over a top surface of the first spacer, and wherein the lateral protrusion of the epi-layer is asymmetrical with respect to the first sidewall and the second sidewall;
a second isolation structure disposed directly over the second spacer;
and
a metal contact disposed on the epi-layer, the metal contact laterally contacting the second isolation structure, the metal contact being not disposed directly over the second spacer.

4 more elements

A semiconductor device, comprising:

a layer that includes a semiconductive material, wherein the layer includes a first fin structure and a second fin structure that each protrude vertically upwards;
a dielectric structure located over the layer, wherein a portion of the dielectric structure is located between the first fin structure and the second fin structure;
a first epi-layer epitaxially grown on the first fin structure, wherein a composition of the first epi-layer is different from a composition of the first fin structure;
a second epi-layer epitaxially grown on the second fin structure, wherein a composition of the second epi-layer is different from a composition of the second fin structure, wherein the second epi-layer is spaced apart from the first epi-layer;
a first spacer and a second spacer located on opposite sidewalls of the first fin structure, wherein the first and second spacers respectively extend continuously along sidewalls of the first fin structure and the first epi-layer, the second spacer being taller than the first spacer;
a third spacer and a fourth spacer located on opposite sidewalls of the second fin structure, wherein the third and fourth spacers respectively extend continuously along sidewalls of the second fin structure and the second epi-layer, the third spacer being taller than the fourth spacer, wherein the second and third spacers are continuous;
wherein:
the first epi-layer protrudes laterally in a first direction away from the second epi-layer;
the second epi-layer protrudes laterally in a second direction away from the first epi-layer, the second direction being opposite the first direction;
and
a lateral dimension of the first epi-layer is greater than a combined lateral dimension of the first spacer and the first fin structure;
an isolation structure located between the first and second epi-layers;
a first metal contact disposed on the first epi-layer;
and
a second metal contact disposed on the second epi-layer, wherein the first and second metal contacts are physically separated from each other by the isolation structure.

12 more elements

A semiconductor device, comprising:

a layer that includes a semiconductive material, the layer including a first fin structure and a second fin structure;
a first isolation structure disposed over the layer;
a first spacer and a second spacer each disposed over the first isolation structure, wherein the first spacer is disposed on a first sidewall of the first fin structure, wherein the second spacer is disposed on a second sidewall of the first fin structure opposite the first sidewall, and wherein the second spacer is taller than the first spacer;
a first epi-layer grown on the first fin structure, the first epi-layer protruding laterally outward toward the first spacer, wherein a first edge of the first epi-layer toward the first spacer is more rounded than a second edge of the first epi-layer toward the second spacer, and wherein the first edge protrudes laterally over a top surface of the first spacer, wherein a composition of the first epi-layer is different from a composition of the first fin structure, wherein the first and second spacers are disposed on sidewalls of the first epi-layer;
a second epi-layer grown on the second fin structure, the second epi-layer protruding laterally opposite the first epi-layer, wherein the second epi-layer does not merge into the first epi-layer, wherein a composition of the second epi-layer is different from a composition of the second fin structure;
a second isolation structure disposed directly over the second spacer;
a first metal contact disposed on the first epi-layer, wherein the first metal contact is not disposed directly over the second spacer;
and
a second metal contact disposed on the second epi-layer, wherein the first and second metal contacts are physically separated from each other.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/941,074Filed 30 Mar 2018
Published: US 2019/0304984 A13 Oct 2019
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10B 10/12
Static random access memory [SRAM] devices: comprising a MOSFET load element
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/0243
Of fin field-effect transistors [FinFET]: using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide…
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]