Memory cells and memory arrays

A memory cell comprising:

• a first transistor supported by a semiconductor base, the semiconductor base comprising monocrystalline semiconductor material;
• a write wordline which includes a gate of the first transistor;
• second and third transistors above the first transistor and vertically stacked one atop the other;
• the first, second and third transistors ascending upwardly relative to the semiconductor base in an order proceeding from the first transistor to the second transistor to the third transistor;
• a semiconductor material pillar extending continuously through both of the second transistor and the third transistor, the semiconductor material pillar having a bottom surface that is elevationally above an upper surface of the semiconductor base and elevationally above an uppermost surface of the first transistor, the semiconductor material pillar having opposing continuously vertical sidewalls throughout an entirety of a vertical length and comprising channel regions and source/drain regions of both the second transistor and the third transistor;
• a charge-storage device electrically coupled with a source/drain region of the first transistor, and electrically coupled with a gate of the second transistor;
• and
• wherein the charge-storage device is a capacitor between a channel region of the second transistor and the gate of the second transistor.