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US 10,854,607 B2Granted
Isolation well doping with solid-state diffusion sources for finFET architectures
AssigneeIntel Corporation
InventorsChia-Hong Jan, Walid M Hafez, Jeng-Ya David Yeh, Hsu-Yu Chang, Neville L Dias, Chanaka D Munasinghe
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Abstract
An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area.
Claims20
An integrated circuit (IC) structure comprising:
- a substrate material comprising silicon;
- a first fin over a first portion of the substrate material, the first fin comprising at least one of silicon or germanium, and the first fin comprising a first region over a second region that is between the first region and the substrate material;
- a first gate stack adjacent to a sidewall of the first region, wherein the first gate stack includes a gate dielectric and a gate electrode;
- a first source and a first drain coupled to the first region;
- and
- a first dielectric material layer comprising an impurity associated with a first conductivity type, the first dielectric material layer adjacent to a sidewall of the second region, wherein the impurity is also present within the second region;
- a second fin over a second portion of the substrate material, the second fin comprising at least one of silicon or germanium, and the second fin including a third region over a fourth region that is between the third region and the substrate material;
- a second gate stack adjacent to a sidewall of the third region, wherein the second gate stack includes a gate dielectric and a gate electrode;
- a second source and a second drain coupled to the third region;
- and
- a second dielectric material layer lacking the impurity, the second dielectric material layer adjacent to a sidewall of the fourth region, wherein the impurity is also absent from the fourth region;
- and
- an isolation dielectric material over a third portion of the substrate material between the first and second portions of the substrate material, wherein the isolation dielectric material is between the first fin and the second fin, and wherein the isolation dielectric material is adjacent to the first dielectric material layer and adjacent to the second dielectric material layer.
10 more elements
A method of fabricating an IC structure, the method comprising:
- receiving a substrate material comprising silicon;
- forming a first fin over a first portion of the substrate material and a second fin over a second portion of the substrate material, wherein the first and second fins each comprise at least one of silicon or germanium;
- forming a first dielectric material layer over a sidewall of the first fin, the first dielectric material layer comprising an impurity;
- forming a second dielectric material layer over a sidewall of the second fin, the second dielectric material layer lacking the impurity;
- forming an isolation dielectric material over the first and second fins;
- recessing the isolation dielectric material and the first dielectric material layer below an upper region of the first fin, retaining the isolation dielectric material and the first dielectric material layer adjacent to a sidewall of a lower region of the first fin;
- recessing the isolation dielectric material and the second dielectric material layer below an upper region of the second fin, retaining the isolation dielectric material and the second dielectric material layer adjacent to a sidewall of a lower region of the second fin;
- forming a first source and a first drain coupled to the upper region of the first fin;
- forming a second source and a second drain coupled to the upper region of the second fin;
- doping the lower region of the first fin to a first conductivity type by thermally driving the impurity into the lower region of the first fin;
- forming a first gate stack adjacent to a sidewall of the upper region of the first fin, wherein the first gate stack includes a gate dielectric and a gate electrode;
- and
- forming a second gate stack adjacent to a sidewall of the upper region of the first fin, wherein the second gate stack includes a gate dielectric and a gate electrode.
10 more elements
Dependencies are inferred from the claim text.