Replacement gate process for FinFET

A device comprising:

• a dielectric isolation layer disposed over a substrate;
• a first semiconductor fin structure and a second semiconductor fin structure disposed over the substrate and at least partially embedded in the dielectric isolation layer;
• and
• a first source/drain feature disposed on the first semiconductor fin structure, the first source/drain feature interfacing with the dielectric isolation layer and having a first height;
• and
• a second source/drain feature disposed on the second semiconductor fin structure without interfacing with dielectric isolation layer, the second source/drain feature having a second height that is different than the first height.

A device comprising:

• an isolation layer disposed over a substrate;
• a first fin structure disposed within the isolation layer, the first fin structure having opposing sidewall surfaces and a top surface extending between the opposing sidewall surfaces, wherein the isolation layer completely covers the opposing sidewalls of the first fin structure;
• a second fin structure disposed within the isolation layer, the second fin structure having opposing sidewall surfaces and a top surface extending between the opposing sidewall surfaces, wherein the isolation layer is disposed along the opposing sidewalls of the second fin structure such that a portion of each sidewall of the second fin structure is free of the isolation layer;
• a first source/drain feature disposed on the top surface of the first fin structure and associated with a first transistor;
• and
• a second source/drain feature disposed on the top surface of the second fin structure, the second source/drain feature associated with a second transistor, the second transistor being different than the first transistor.