Offset gate contact
AssigneeQUALCOMM Incorporated
InventorsChihWei Kuo, Haining Yang, Jun Yuan, Kern Rim
Life of this patent
Estimating the term…
Abstract
Offsetting or modulating the location of a gate between two transistors may achieve a lower power circuit and a higher speed circuit depending on the new location of the gate. In one example, a gate between a PFET transistor and an NFET transistor may be offset towards the PFET transistor to achieve a higher speed circuit than a conventional circuit with the gate located equal distance between the transistors. In another example, a gate between a PFET transistor and an NFET transistor may be offset towards the NFET transistor to achieve a lower power circuit than a conventional circuit with the gate located equal distance between the transistors.
Claims20
A circuit comprising:
- a first transistor coupled to a supply voltage, the first transistor comprising a gate region, a source contact, and a drain contact;
- a second transistor coupled to a ground, the second transistor comprising a gate region, a source contact, and a drain contact;
- and
- a first gate coupled to the first transistor and the second transistor at a first location, wherein the first location is offset from a center point between the first transistor and the second transistor.
A circuit comprising:
- a first means for amplifying coupled to a supply voltage, the first means for amplifying comprising a gate region, a source contact, and a drain contact;
- a second means for amplifying coupled to a ground, the second means for amplifying comprising a gate region, a source contact, and a drain contact;
- and
- a first gate coupled to the first means for amplifying and the second means for amplifying at a first location, wherein the first location is offset from a center point between the first means for amplifying and the second means for amplifying.
A method for forming a circuit, the method comprising:
- forming a gate region, a source contact, and a drain contact of a first transistor;
- forming a gate region, a source contact, and a drain contact of a second transistor;
- and
- forming a first gate coupled to the first transistor and the second transistor at a first location, wherein the first location is offset from a center point between the first transistor and the second transistor.
Dependencies are inferred from the claim text.