Integrated enhancement mode and depletion mode device structure and method of making the same

A method of forming an integrated circuit comprising:

• forming a heterostructure over a substrate structure;
• forming an isolation region on the heterostructure to electrically isolate an e-mode device area from a d-mode device area of the heterostructure;
• etching a castellated channel region in the e-mode device area of the heterostructure to define a plurality of ridge channels interleaved between a plurality of trenches, wherein each trench of the plurality of trenches exposes a top planar semiconductor surface of the substrate structure between neighboring ridge channels of the plurality of ridge channels;
• depositing a mask over the castellated channel region in the e-mode device area and a single planar gate region in the d-mode device area of the heterostructure;
• etching the mask to provide a castellated gate opening in the the castellated channel region, wherein the etching of the mask further provides a planar gate opening in the single planar gate region;
• and
• performing a contact fill with a conductive material of the castellated gate opening to form a castellated gate contact that extends across the castellated channel region and substantially surrounds each of the plurality of ridge channels around their top and their sides to overlap a channel interface of the heterostructure of each of the plurality of ridge channels, such that the castellated gate contact extends along at least a portion of a length of each ridge channel.