CMOS RF power limiter and ESD protection circuits

A radio frequency (RF) power limiter circuit and ESD protection circuit for limiting the power of a symmetrical RF input signal and protecting against voltage spikes, the circuit amenable for fabrication in a CMOS technology, the RF power limiter circuit and ESD protection circuit comprising:

• a P-type Silicon substrate with a first and second planar P-well regions formed on a front surface of the substrate wherein each P-well region is surrounded by an N-well region and a deep N-well spans the region beneath the P-well and the N-well regions;
• an input terminal and a ground terminal both affixed to the front surface of the substrate;
• a first NMOS field effect transistor (FET) formed in the first P-well region and a second NMOS FET formed in the second P-well region, wherein the two NMOS FETs are each configured to perform a diode function with a defined forward voltage and are arranged in an anti-parallel configuration and coupled between the input terminal and the ground terminal;
• a first resistor connected between the ground terminal and an Ohmic contact to the first P-well and a second resistor connected between the input terminal and an Ohmic contact to the second P-well;
• a first shunt wire connecting the ground terminal and the gate electrode and the drain terminal of the first NMOS FET and a second shunt wire connecting the input terminal and the gate electrode and the drain terminal of the second NMOS FET;
• a third resistor connecting the ground terminal to the source terminal of the second NMOS FET and a fourth resistor connecting the input terminal to the source terminal of the first NMOS FET;
• and
• a third shunt wire connecting the ground terminal to one or more P+ doped contact regions formed in the N-well regions and a fourth shunt wire connecting the input terminal to different P+ doped contact region formed in the N-well regions, wherein an RF signal applied symmetrically to the input terminal and ground terminal becomes symmetrically attenuated when the signal level exceeds the defined forward voltage of the diode configured NMOS FETs and wherein an ESD signal in excess of a designed value is attenuated by action of a grounded gate NMOS FET.