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US 10,854,591 B2Granted
Semiconductor device including a repeater/buffer at upper metal routing layers and methods of manufacturing the same
AssigneeSamsung Electronics Co., Ltd.
InventorsWei-E Wang, Titash Rakshit, Borna J. Obradovic, Chris Bowen, Mark S. Rodder
Life of this patent
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Abstract
A semiconductor device includes a series of metal routing layers and a complementary pair of planar field-effect transistors (FETs) on an upper metal routing layer of the metal routing layers. The upper metal routing layer is M3 or higher. Each of the FETs includes a channel region of a crystalline material. The crystalline material may include polycrystalline silicon. The upper metal routing layer M3 or higher may include cobalt.
Claims10
A semiconductor device comprising:
- metal routing layers M1 to Ma, a being an integer selected from 4 or greater, the metal routing layers stacking up from M1 in a thickness direction;
- a complementary pair of planar field-effect transistors (FETs) on metal routing layer Mb, b being smaller than a and selected from 3 or greater;
- a first inter-layer dielectric layer comprising a first inter-layer dielectric material and between the metal routing layer Mb and the complementary pair of FETs,
- a crystalline material layer comprising a polycrystalline material and formed on the first inter-layer dielectric material,
- a second inter-layer dielectric layer comprising a second inter-layer dielectric material and between the complementary pair of FETs and metal routing layer M(b+1), and
- metal vias through the second inter-layer dielectric layer,
- wherein each of the FETs comprises a channel region formed of the polycrystalline material,
- wherein the complementary pair of FETs are between the metal routing layer Mb and metal routing layer M(b+1),
- wherein the channel region formed of the polycrystalline material is directly on the first inter-layer dielectric layer, and the polycrystalline material comprises polycrystalline silicon,
- wherein the FETs are arranged in a repeater/buffer circuit consisting of one level of via or no vias,
- wherein each of the FETs further comgrises source and drain electrodes comprising the polycrystalline material, a gate insulation layer on the crystalline material layer, a gate electrode on the gate insulation layer, low temperature contacts in direct contact with the source and drain electrodes and comprising Ti, Ni, Pt, and/or Co, and a gate spacer between the gate electrode and the low temperature contacts, the gate spacer comprising a nitride and in direct contact with the low temperature contacts, and
- the metal vias connect the low temperature contacts with the metal routing layer M(b+1).
9 more elements
A semiconductor device comprising:
- metal routing layers M1 to Ma, a being an integer selected from 4 or greater, the metal routing layers stacking up from M1 in a thickness direction;
- a complementary pair of planar field-effect transistors (FETs) on metal routing layer Mb, b being smaller than a and selected from 3 or greater,
- a first inter-layer dielectric layer comprising a first inter-layer dielectric material and between the metal routing layer Mb and the complementary pair of planar FETs,
- a crystalline material layer comprising a polycrystalline material and formed on the first inter-layer dielectric material,
- a second inter-layer dielectric layer comprising a second inter-layer dielectric material and between the complementary pair of FETs and metal routing layer M (b+1 ), and
- metal vias through the second inter-layer dielectric layer,
- wherein each of the FETs comprises a channel region formed of the polycrystalline material, and
- wherein the complementary pair of planar FETs are between the metal routing layer Mb and metal routing layer M(b+1)
- wherein each FET of the pair of planar FETs further comprises source and drain regions comprising the polycrystalline material of the channel region,
- wherein each FET further comprises a pair of metal regions comprising Ti, Ni, Pt, and/or Co, and directly contacting the source and drain regions with regular salicide formation between the pair of metal regions and the source and drain regions,
- wherein each FET further comprises a gate insulation layer on the crystalline material layer, a gate electrode on the gate insulation layer, and a gate spacer between the gate electrode and the pair of metal regions, the gate spacer comprising a nitride and in direct contact with the pair of metal regions,
- wherein the FETs are arranged in a repeater/buffer circuit consisting of one level of via or no vias, and
- wherein the metal vias connect the pair of metal regions with the metal routing layer M(b+1).
10 more elements
Dependencies are inferred from the claim text.