Semiconductor package with improved power integrity

A semiconductor package, comprising:

• a connection member having a first surface and a second surface opposing each other, and including a redistribution layer;
• an integrated circuit chip disposed on the first surface of the connection member, having a connection electrode connected to the redistribution layer, and including a plurality of units;
• a plurality of capacitors disposed on the first surface of the connection member and adjacent to the integrated circuit chip;
• and
• an encapsulant disposed on the first surface of the connection member and encapsulating the integrated circuit chip and the plurality of capacitors,
• wherein the plurality of units includes a first unit having a first power consumption rate and disposed adjacent to one edge of the integrated circuit chip, and a second unit having a second power consumption rate lower than the first power consumption rate and disposed further inward on the integrated circuit chip than the first unit, and
• the plurality of capacitors is disposed adjacent to the one edge of the integrated circuit chip.

A semiconductor package, comprising:

• an integrated circuit chip comprising a first core power unit disposed adjacent to a first edge of the integrated circuit chip and a first other unit, the integrated circuit chip being disposed on a first surface of a connection member;
• a capacitor disposed on the first surface of the connection member and adjacent to the first edge of the integrated circuit chip;
• and
• an encapsulant disposed on the first surface of the connection member and encapsulating at least a portion of each of the integrated circuit chip and the capacitor,
• wherein the connection member comprises a wiring layer directly connecting the first core power unit and the capacitor.