Diffused bitline replacement in stacked wafer memory
AssigneeInvensas Corporation
InventorStephen Morein
Life of this patent
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Abstract
Techniques are disclosed herein for creating metal BLs in stacked wafer memory. Using techniques described herein, metal BLs are created on a bottom surface of a wafer. The metal BLs can be created using different processes. In some configurations, a salicide process is utilized. In other configurations, a damascene process is utilized. Using metal reduces the resistance of the BLs as compared to using non-metal diffused BLs. In some configurations, wafers are stacked and bonded together to form three-dimensional memory structures.
Claims18
A memory array comprising:
- a wafer;
- a transistor array disposed in the wafer such that source regions of the transistor array are closer to a first side of the wafer than drain regions of the array, and drain regions of the transistor array are closer to a second side of the wafer than the source regions of the array;
- metal bitlines coupled to the source regions;
- memory cells coupled to the drain regions;
- a second wafer that includes a first surface and a second surface;
- and
- a second transistor array in the second wafer, the second transistor array having memory cells coupled to a first side of the second transistor array and metal bitlines coupled a second side of the second transistor array, the second wafer mechanically and electrically coupled to the first wafer.
A method to create a memory array, comprising:
- forming an array of transistors in a wafer such that source regions of the array are closer to a first side of the wafer than drain regions of the array, and drain regions of the array are closer to a second side of the wafer than the source regions of the array;
- forming an array of memory cells coupled to the drain regions;
- forming metal bitlines coupled to the source regions;
- forming a second array of transistors in a second wafer such that source regions of the second array are closer to a first side of the second wafer than drain regions of the second array, and drain regions of the second array are closer to a second side of the second wafer than the source regions of the second array;
- forming a second array of memory cells coupled to the drain regions of the second array;
- forming second metal bitlines coupled to the source regions of the second array;
- and
- bonding the wafer to the second wafer.
A memory device comprising:
- a transistor array that includes a first transistor surface and a second transistor surface, wherein transistors of the transistor array are electrically coupled to the metal bitlines via the second transistor surface;
- metal bitlines coupled to the second transistor surface;
- memory cells coupled to the first transistor surface;
- a second transistor array that includes a first transistor surface and a second transistor surface;
- second metal bitlines coupled to the second transistor surface;
- and
- second memory cells electrically coupled to the first surface of the second transistor array, wherein the second transistor array is stacked and electrically coupled to the first transistor array.
Dependencies are inferred from the claim text.