Integrated fan-out package and method of fabricating the same

A method of fabricating an integrated fan-out package, comprising:

• forming a redistribution circuit structure along a build-up direction on a substrate, wherein forming the redistribution circuit structure comprises:
• forming a plurality of conductive wirings on the substrate;
• forming a plurality of conductive vias and a dielectric layer covering the plurality of conductive wirings, a lateral dimension of each of the conductive vias decreases from a first end to a second end along the build-up direction, wherein the first end is facing the substrate and the second end is opposite to the first end facing away from the substrate;
• forming a plurality of conductive bumps on the redistribution circuit structure electrically connected to the plurality of conductive vias;
• forming solder caps on the plurality of conductive bumps;
• after forming the redistribution circuit structure, the plurality of conductive bumps and the solder caps, providing an integrated circuit component having a plurality of conductive pillars over the redistribution circuit structure, and bonding the plurality of conductive pillars of the integrated circuit component to the conducive bumps on the redistribution circuit structure through the solder caps;
• and
• forming an insulating encapsulation between the redistribution circuit structure and the integrated circuit component, wherein the insulating encapsulation encapsulates and is in physical contact with the conductive bumps, the solder caps and the conductive pillars.

An integrated fan-out package, comprising:

• an integrated circuit component, wherein the integrated circuit component comprises conductive pillars having lateral dimensions that increases along a build-up direction;
• an insulating encapsulation laterally encapsulating sidewalls of the integrated circuit component;
• a redistribution circuit structure, comprising:
• a plurality of conductive vias embedded in a dielectric layer, wherein a lateral dimension of each of the conductive vias decreases from a first end to a second end along the build-up direction, and the first end is located in between the second end and the integrated circuit component, and a first surface of at least one of the plurality of conductive vias having the greatest lateral dimension of the plurality of conductive vias is directly connected to a second surface of the conductive pillars having the greatest lateral dimension of the conductive pillars;
• and
• a plurality of conductive wirings disposed on the plurality of conductive vias and the dielectric layer.