Package structure, semiconductor device and method of fabricating the same

A semiconductor device, comprising:

• a first semiconductor die having first conductive posts;
• a second semiconductor die having second conductive posts;
• a first seed layer located on the first conductive posts of the first semiconductor die, and on the second conductive posts of the second semiconductor die;
• a plurality of conductive pillars located on the first seed layer;
• a second seed layer covering the plurality of conductive pillars, wherein the second seed layer is physically separated from the first seed layer;
• an insulating encapsulant surrounding the first semiconductor die and the second semiconductor die, wherein the insulating encapsulant has an upper surface that is aligned with top surfaces of the first conductive posts and the second conductive posts, and the upper surface has recesses adjacent to the top surfaces of the first conductive posts and the second conductive posts;
• and
• a redistribution layer disposed on the second seed layer, and electrically connected to the first semiconductor die and the second semiconductor die through the plurality of conductive pillars.

A method of fabricating a semiconductor device, comprising:

• disposing a plurality of semiconductor dies on a carrier, wherein the plurality of semiconductor dies has a plurality of conductive posts;
• forming an insulating encapsulant surrounding the plurality of semiconductor dies;
• forming a first seed layer on the plurality of conductive posts after forming the insulating encapsulant;
• forming a plurality of conductive pillars on the first seed layer;
• forming an insulating layer over the insulating encapsulant to surround the plurality of conductive pillars and the first seed layer;
• forming a second seed layer covering the plurality of conductive pillars after forming the insulating layer, wherein the second seed layer is physically separated from the first seed layer;
• and
• forming a redistribution layer over the second seed layer, wherein the redistribution layer is electrically connected to the plurality of semiconductor dies through the plurality of conductive pillars.