Chip package structure with bump

A chip package structure, comprising:

• a first chip structure between a second chip structure and a redistribution structure;
• a first molding layer surrounding the first chip structure;
• a second molding layer surrounding the second chip structure;
• conductive bumps between the redistribution structure and the first chip structure;
• and
• a third molding layer extending over sidewalls of the first molding layer and the second molding layer, wherein a bottom surface of the third molding layer is between the redistribution structure and a bottom surface of the first molding layer.

A chip package structure, comprising:

• a redistribution substrate;
• a first chip structure over the redistribution substrate;
• a first molding layer surrounding the first chip structure, wherein the first molding layer and the first chip structure are spaced apart from the redistribution substrate, and the first molding layer is in direct contact with the first chip structure;
• a second chip structure over the first chip structure;
• a second molding layer surrounding the second chip structure;
• a conductive via structure passing through the first molding layer and electrically connected to the second chip structure;
• and
• a third molding layer surrounding the first molding layer and the second molding layer, wherein the third molding layer is partially between the first molding layer and the redistribution substrate and partially between the first chip structure and the redistribution substrate.