Method of manufacturing mark
AssigneePowerchip Semiconductor Manufacturing Corporation
InventorsHsiao-Chiang Lin, Chia-Kuang Lee, Shih-Ci Yen
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AssigneePowerchip Semiconductor Manufacturing Corporation
InventorsHsiao-Chiang Lin, Chia-Kuang Lee, Shih-Ci Yen
Estimating the term…
A method of manufacturing a mark including the following steps is provided. A substrate including a device area and a mark area is provided. A dielectric layer is formed on the substrate. A dual damascene opening is formed in the dielectric layer of the device area. The dual damascene opening includes a first opening and a second opening connected to each other. The width of the second opening is greater than the width of the first opening. A third opening is formed in the dielectric layer of the mark area. The third opening and the first opening are simultaneously formed by the same process. A barrier material layer is formed on the surfaces of the dual damascene opening and the third opening. The barrier material layer seals the third opening to form a void in the third opening. A metal material layer is formed on the barrier material layer.
A method of manufacturing a mark, comprising:
Dependencies are inferred from the claim text.