Semiconductor package and method of fabricating the same
AssigneeSamsung Electronics Co., Ltd.
InventorsHae-Jung Yu, Kyung Suk Oh
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface, a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer, a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip, and a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals.
Claims18
A semiconductor package, comprising:
- a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads and a plurality of second redistribution pads on the first surface, the plurality of second redistribution pads having a pitch different from a pitch of the plurality of first redistribution pads;
- a semiconductor chip on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer;
- a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip;
- and
- a plurality of external connection terminals on and coupled to the conductive structures, the plurality of external connection terminals having a non-overlapping relationship with respect to the semiconductor chip, in a top view, and the pitch of the plurality of first redistribution pads being smaller than a pitch of the plurality of external connection terminals.
A semiconductor package, comprising:
- a redistribution layer having a first surface and a second surface opposite to each other, the redistribution layer including a plurality of first redistribution pads on the first surface;
- a plurality of base layers on the second surface of the redistribution layer, a hole penetrating the plurality of base layers;
- a semiconductor chip inside the hole on the second surface of the redistribution layer, an active surface of the semiconductor chip facing the redistribution layer;
- a plurality of conductive structures on the second surface of the redistribution layer, the plurality of conductive structures being spaced apart from the semiconductor chip;
- a plurality of external connection terminals on and coupled to the conductive structures, the plurality of first redistribution pads have a pitch smaller than a pitch of the plurality of external connection terminals,
- wherein at least one of the conductive structures includes:
- a first pad on an uppermost one of the plurality of base layers;
- a conductive pattern between two base layers of the plurality of base layers;
- a via penetrating each one of the plurality of base layers, the via being coupled to the conductive pattern;
- and
- a second pad on a lowermost one of the plurality of base layers, the second pad being horizontally offset with respect to the first pad.
A semiconductor package, comprising:
- a redistribution layer having a first surface and a second surface opposite to each other;
- a semiconductor chip on the second surface of the redistribution layer, the semiconductor chip including a chip pad facing the redistribution layer;
- a plurality of conductive structures on the second surface of the redistribution layer and spaced apart from the semiconductor chip;
- a first semiconductor device including a first semiconductor chip on the first surface of the redistribution layer, the first semiconductor device including Hail at least three connection pads facing the redistribution layer;
- and
- a plurality of first redistribution pads on the first surface of the redistribution layer, the plurality of first redistribution pads being connected to the connection pads, respectively, and the plurality of first redistribution pads having a non-vertically overlapping relationship with the semiconductor chip.
Dependencies are inferred from the claim text.