Anti-fuse structure circuit and forming method thereof
AssigneesSemiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
InventorJunhong Feng
Life of this patent
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Abstract
Anti-fuse structure circuit and method of forming an anti-fuse structure circuit are provided. A substrate is provided, and an anti-fuse is formed on the substrate by forming a first gate structure and a dielectric layer on the substrate and forming conductive plugs respectively in the dielectric layer at two sides of the first gate structure. The dielectric layer covers the first gate structure, and the conductive plugs have a width decreasing from top to bottom. A second gate structure is formed on the substrate. A top surface of the first gate structure is higher than a top surface of the second gate structure. The dielectric layer also covers the second gate structure. The conductive plugs are also located respectively in the dielectric layer at two sides of the second gate structure.
Claims20
A method of forming an anti-fuse structure circuit, comprising:
- providing a substrate;
- forming an anti-fuse on the substrate by a process including
- forming a first gate structure and a dielectric layer on the substrate, the dielectric layer covering the first gate structure, and forming conductive plugs respectively in the dielectric layer at two sides of the first gate structure, the conductive plugs having a width decreasing from top to bottom;
- and
- forming a second gate structure on the substrate, wherein a top surface of the first gate structure is higher than a top surface of the second gate structure, the dielectric layer also covers the second gate structure, and the conductive plugs are also located respectively in the dielectric layer at two sides of the second gate structure.
An anti-fuse structure circuit, comprising:
- a substrate;
- an anti-fuse, including a first gate structure and a dielectric layer that are located on the substrate, the dielectric layer covering the first gate structure, and conductive plugs located respectively in the dielectric layer at two sides of the first gate structure, the conductive plugs having a width decreasing from top to bottom;
- and
- a second gate structure located on the substrate, wherein a top surface of the first gate structure is higher than a top surface of the second gate structure, the dielectric layer also covers the second gate structure, and the conductive plugs are also located respectively in the dielectric layer at two sides of the second gate structure.
Dependencies are inferred from the claim text.