Via structure and methods thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChe-Cheng Chang, Chih-Han Lin
Life of this patent
Estimating the term…
Abstract
A method includes providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate; forming a buffer layer over the substrate; forming a dielectric layer over the buffer layer; performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer; and performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening.
Claims20
A method, comprising:
- providing a substrate, wherein the substrate includes a conductive feature in a top portion of the substrate;
- forming a buffer layer over the substrate;
- forming a dielectric layer over the buffer layer;
- performing a first etching process to form an opening in the dielectric layer, thereby exposing a top surface of the buffer layer;
- and
- performing a second etching process to extend the opening downwardly into the buffer layer, thereby exposing a top surface of the conductive feature, wherein the performing of the second etching process includes laterally enlarging a footing profile of the opening
- wherein the performing of the first etching process forms sidewalls of the opening tapered inwardly towards a center of the opening, and the performing of the second etching process extends the sidewalls of the opening outwardly away from the center of the opening.
A method of forming a semiconductor device, comprising:
- forming a first etch stop layer over a substrate;
- forming a second etch stop layer over the first etch stop layer, wherein the second and first etch stop layers include different material compositions;
- forming a low-k dielectric layer over the second etch stop layer;
- and
- forming a via extending through the low-k dielectric layer, the second etch stop layer, and the first etch stop layer, wherein the via has a top sidewall tapered inwardly towards a center of the via and a bottom sidewall tapered outwardly away from the center of the via, wherein the top sidewall and the bottom sidewall intersect below a top surface of the second etch stop layer.
A method of fabricating an integrated circuit, comprising:
- depositing a buffer layer over a substrate;
- depositing a dielectric layer over the buffer layer;
- removing a portion of the dielectric layer to form an opening;
- etching the buffer layer through the opening, thereby extending the opening through the buffer layer and exposing a top surface of the substrate in the opening, wherein the etching of the buffer layer includes an isotropic etching or a lateral etching, and wherein after the etching of the buffer layer, a cross section of the opening that has a smallest cross-sectional area is located below a top surface of the buffer layer and above the top surface of the substrate;
- and
- filling the opening with a conductive feature.
Dependencies are inferred from the claim text.