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US 10,854,531 B2Granted
Semiconductor packaging method, semiconductor package and stacked semiconductor packages
AssigneePep Innovation Pte. Ltd.
InventorYi Xin Chew
Life of this patent
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Abstract
A semiconductor packaging method, a semiconductor package and stacked semiconductor packages are provided. The method includes providing a carrier (10) having a plurality of semiconductor chip receiving areas (12) and attaching a plurality of first semiconductor chips (14) to the semiconductor chip receiving areas (12). The first semiconductor chips (14) are encapsulated with a first encapsulant (20) and a plurality of electrical connections (24) is formed to the first semiconductor chips (14). At least a portion of the carrier (10) is removed to provide a heat release area (38).
Claims10
A semiconductor package, comprising:
- a first semiconductor chip having a plurality of circuit pads;
- an electrically conductive layer provided over at least one of the circuit pads of the first semiconductor chip;
- a first encapsulant encapsulating the first semiconductor chip;
- a plurality of electrical connections to the first semiconductor chip, wherein the electrical connections to the first semiconductor chip comprises:
- a plurality of vias extending through the first encapsulant to the first semiconductor chip, wherein a cross-sectional area of the vias is smaller than a surface area of the electrically conductive layer formed over the at least one of the circuit pads of the first semiconductor chip;
- and
- a plurality of first traces on a surface of the first encapsulant, wherein the first traces are electrically connected by the vias to the first semiconductor chip;
- a heat release area arranged to release heat generated by the first semiconductor chip, wherein the heat release area comprises one of:
- a surface of a conductive layer to which a die pad is attached, wherein the first semiconductor chip is attached to the die pad;
- a surface of a conductive layer to which the first semiconductor chip is attached;
- a surface area of a heat sink attached to a conductive layer, wherein the first semiconductor chip is attached to the conductive layer;
- a surface area of an array of heat sinks attached to a conductive layer, wherein the first semiconductor chip is attached to the conductive layer;
- a surface area of a plurality of fins attached to a conductive layer, wherein the first semiconductor chip is attached to the conductive layer;
- and
- a surface area of a heat sink attached to a conductive layer to which a die pad is attached, wherein the first semiconductor chip is attached to the die pad;
- a plurality of connectors encapsulated by the first encapsulant;
- and
- a plurality of openings formed in the conductive layer, the openings exposing a surface of the connectors.
15 more elements
Dependencies are inferred from the claim text.