Heat dissipation structures
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYun-Wei Cheng, Chun-Hao Chou, Kuo-Cheng Lee, Ying-Hao Chen
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Abstract
The present disclosure describes heat dissipation structures formed in functional or non-functional areas of a three-dimensional chip structure. These heat dissipation structures are configured to route the heat generated within the three-dimensional chip structure to designated areas on or outside the three-dimensional chip structure. For example, the three-dimensional chip structure can include a plurality of chips vertically stacked on a substrate, a first passivation layer interposed between a first chip and a second chip of the plurality of chips, and a heat dissipation layer embedded in the first passivation layer and configured to allow conductive structures to pass through.
Claims20
A stacked structure, comprising:
- a plurality of chips vertically stacked on a substrate;
- a first passivation layer interposed between a first chip and a second chip of the plurality of chips;
- electrically conductive structures traversing through the first passivation layer and electrically connecting the first and second chips;
- thermally conductive structures traversing through the first passivation layer between the first and second chips;
- and
- a heat dissipation layer embedded in the first passivation layer configured to allow the thermally conductive structures and the electrically conductive structures to pass through, wherein the thermally conductive structures are in contact with the heat dissipation layer and the electrically conductive structures are isolated from the heat dissipation layer.
A structure, comprising:
- a plurality of vertically stacked chips bonded together through respective passivation layers;
- a first heat dissipation layer embedded in a first passivation layer and configured to allow conductive structures to pass through;
- a second heat dissipation layer embedded in a second passivation layer and comprising a first array of heat dissipating stripes disposed on a second array of heat dissipating stripes;
- and
- a third heat dissipation layer disposed in a metallization layer of one of the vertically stacked chips.
A stacked structure, comprising:
- a first chip, a second chip, and a third chip vertically stacked on a substrate, wherein the second chip is interposed between the first and third chips;
- a first heat dissipation layer embedded in a passivation layer disposed between the first and second chips, wherein the first heat dissipation layer comprises stacked layers of heat dissipating stripes;
- and
- a second heat dissipation layer integrated in the third chip and configured to allow conductive structures of the third chip to pass through.
Dependencies are inferred from the claim text.