Semiconductor package including organic interposer
AssigneeSamsung Electronics Co., Ltd.
InventorsJun Woo Myung, Akihisa Kuroyanagi, Yeong A Kim, Eun Sil Kim
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Abstract
A semiconductor package including an organic interposer includes: first and second semiconductor chips each having active surfaces having connection pads disposed thereon; the organic interposer disposed on the active surfaces of the first and second semiconductor chips and including a wiring layer electrically connected to the connection pads; barrier layers disposed on side surfaces of the first and second semiconductor chips; and an encapsulant encapsulating at least portions of the first and second semiconductor chips.
Claims20
A semiconductor package, comprising:
- at least one semiconductor chip having an active surface on which connection pads are disposed;
- wiring layers electrically connected to the connection pads by connection members;
- insulating layers covering at least portions of the wiring layers;
- an underfill resin disposed between the at least one semiconductor chip and the insulating layers;
- a barrier layer covering outer side surfaces of the at least one semiconductor chip;
- and
- an encapsulant encapsulating at least a portion of the at least one semiconductor chip,
- wherein the barrier layer is formed of a material having a coefficient of thermal expansion (CTE) different from a CTE of the encapsulant.
A semiconductor package, comprising:
- at least one semiconductor chip having an active surface on which connection pads are disposed;
- wiring layers electrically connected to the connection pads;
- photoimagable dielectric layers covering at least portions of the wiring layers;
- an underfill resin disposed between the at least one semiconductor chip and the photoimagable dielectric layers;
- an encapsulant encapsulating at least a portion of the at least one semiconductor chip;
- and
- a barrier layer disposed between the at least one semiconductor chip and the encapsulant,
- wherein the barrier layer is formed of a material having a coefficient of thermal expansion (CTE) higher than a CTE of the at least one semiconductor chip and lower than a CTE of the encapsulant.
Dependencies are inferred from the claim text.