Method for processing a semiconductor wafer using non-contact electrical measurements indicative of at least one tip-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective tip-to-side short, corner short, and via open test areas

A method for processing a semiconductor wafer, comprising at least the following acts:

• patterning a tip-to-side short-configured test area on the wafer;
• patterning a first non-contact electrical measurement (NCEM) pad on the wafer;
• patterning one or more connections to (i) electrically connect a first portion of the tip-to-side short-configured test area to the first NCEM pad and (ii) electrically connect a second portion of the tip-to-side short-configured test area to a permanent or virtual ground;
• patterning a corner short-configured test area on the wafer;
• patterning a second NCEM pad on the wafer;
• patterning one or more connections to (i) electrically connect a first portion of the corner short-configured test area to the second NCEM pad and (ii) electrically connect a second portion of the corner short-configured test area to a permanent or virtual ground;
• patterning a via open-configured test area on the wafer;
• patterning a third NCEM pad on the wafer;
• patterning one or more connections to (i) electrically connect a first portion of the via open-configured test area to the third NCEM pad and (ii) electrically connect a second portion of the via open-configured test area to a permanent or virtual ground;
• obtaining one or more first inline non-contact electrical measurements (inline NCEMs) from the first NCEM pad, where each first inline NCEM provides a measurement indicative of a short or leakage in the tip-to-side short-configured test area;
• obtaining one or more second inline NCEMs from the second NCEM pad, where each second inline NCEM provides a measurement indicative of a short or leakage in the corner short-configured test area;
• and,
• obtaining one or more third inline NCEMs from the third NCEM pad, where each third inline NCEM provides a measurement indicative of an open or resistance in the via open-configured test area.