US 10,854,513 B2Granted

Cavity-disrupting backside trench fill structures for a three-dimensional memory device and method of making the same

AssigneeSanDisk Technologies LLC

InventorsMotoki Kawasaki, Toshiyuki Sega

Life of this patent

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Abstract

An alternating stack of insulating layers and sacrificial material layers is formed over a semiconductor material layer. Memory stack structures are formed through the alternating stack. A backside trench is formed through the alternating stack. The sacrificial material layers are replaced with electrically conductive layers. An insulating spacer is formed on sidewalls of the backside trench. A first doped semiconductor material is deposited within the backside trench. Vertical cavities are formed by vertically recessing the first doped semiconductor material at discrete locations that are laterally spaced apart. A second doped semiconductor material is deposited in the vertical cavities. The second doped semiconductor material disrupts a laterally-extending cavity in the first doped semiconductor material, thereby providing a structurally reinforced network of the first and second doped semiconductor materials for a backside contact via structure that is formed in the backside trench.

Claims20

Dependent claims

A three-dimensional memory device, comprising:

alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, wherein a neighboring pair of alternating stacks are laterally spaced apart from each other by a backside trench that laterally extends along a first horizontal direction;
memory stack structures vertically extending through a respective one of the alternating stacks and comprising a respective vertical semiconductor channel;
an insulating spacer contacting sidewalls of the backside trench;
and
a backside contact via structure located within the insulating spacer and comprising:
at least one first doped semiconductor material portion comprising a first semiconductor material located within a volume laterally surrounded by the insulating spacer;
and
at least one second doped semiconductor material portion comprising a second semiconductor material and located within the volume,
wherein the backside contact via structure has at least one feature selected from:
(i) the second semiconductor material has a different material composition than the first semiconductor material;
or
(ii) an interfacial semiconductor oxide layer having a thickness that provides conductive electrical contact thereacross is located at an interface between each neighboring pair of the at least one first doped semiconductor material portion and the at least one second doped semiconductor material portion,
wherein the three-dimensional memory device has at least one feature selected from:
(A) a ratio of a total area of the at least one first doped semiconductor material portion relative to a total area of a vertical cross-sectional shape of the backside contact via structure within each of vertical cross-sectional planes that are perpendicular to the first horizontal direction varies as a function of a lateral distance of a respective vertical cross-sectional plane from a reference plane that is perpendicular to the first horizontal direction;
or
(B) an elongated section of the backside contact via structure is located between a first horizontal plane including bottom surfaces of a topmost electrically conductive layer within the alternating stacks and a second horizontal plane including top surfaces of the topmost electrically conductive layer within the alternating stacks;
and
the elongated section has a lateral compositional modulation along the first horizontal direction such that portions consisting of the at least one first doped semiconductor material alternate with portions consisting of the at least one second doped semiconductor material.

15 more elements

A three-dimensional memory device, comprising:

alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, wherein a neighboring pair of alternating stacks are laterally spaced apart from each other by a backside trench that laterally extends along a first horizontal direction;
memory stack structures vertically extending through a respective one of the alternating stacks and comprising a respective vertical semiconductor channel;
an insulating spacer contacting sidewalls of the backside trench;
and
a backside contact via structure located within the insulating spacer and comprising:
at least one first doped semiconductor material portion comprising a first semiconductor material located within a volume laterally surrounded by the insulating spacer;
and
at least one second doped semiconductor material portion comprising a second semiconductor material and located within the volume,
wherein the backside contact via structure has at least one feature selected from:
the second semiconductor material has a different material composition than the first semiconductor material;
or
an interfacial semiconductor oxide layer having a thickness that provides conductive electrical contact thereacross is located at an interface between each neighboring pair of the at least one first doped semiconductor material portion and the at least one second doped semiconductor material portion,
wherein:
(C) the three-dimensional memory device further comprises voids that are bounded entirely by surfaces of the second semiconductor material, are encircled by the at least one first doped semiconductor material portion in a vertical cross-sectional view, and are spaced from the at least one first doped semiconductor material portion by the at least one second doped semiconductor material portion;
or
(D) the at least one first doped semiconductor material portion comprises a plurality of first discrete doped semiconductor material portions that are laterally spaced apart by the at least one second doped semiconductor material portion;
and
the at least one second doped semiconductor material portion contacts three or more of the plurality of first discrete doped semiconductor material portions that are laterally spaced apart along the first horizontal direction.

15 more elements

A three-dimensional memory device, comprising:

alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, wherein a neighboring pair of alternating stacks are laterally spaced apart from each other by a backside trench that laterally extends along a first horizontal direction;
memory stack structures vertically extending through a respective one of the alternating stacks and comprising a respective vertical semiconductor channel;
an insulating spacer contacting sidewalls of the backside trench;
and
a backside contact via structure located within the insulating spacer and comprising:
at least one first doped semiconductor material portion comprising a first semiconductor material located within a volume laterally surrounded by the insulating spacer;
and
at least one second doped semiconductor material portion comprising a second semiconductor material and located within the volume,
wherein the backside contact via structure has at least one feature selected from:
the second semiconductor material has a different material composition than the first semiconductor material;
or
an interfacial semiconductor oxide layer having a thickness that provides conductive electrical contact thereacross is located at an interface between each neighboring pair of the at least one first doped semiconductor material portion and the at least one second doped semiconductor material portion,
wherein:
(E) the at least one first doped semiconductor material portion comprises a plurality of first discrete doped semiconductor material portions that are laterally spaced apart by the at least one second doped semiconductor material portion;
and
the at least one second doped semiconductor material portion comprises a plurality of second discrete doped semiconductor material portions that are interlaced with, and alternate along the first horizontal direction with, the plurality of first discrete doped semiconductor material portions;
or
(F) the backside contact via structure comprises a first metallic liner that includes:
a horizontal portion that contacts the semiconductor material layer and the at least one first doped semiconductor material portion;
and
vertical portions that contact inner sidewalls of the insulating spacer, the at least one first doped semiconductor material portion, and the at least one second doped semiconductor material portion.

18 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/249,352Filed 16 Jan 2019
Published: US 2020/0227318 A116 Jul 2020
Granted: 1 Dec 2020
Term ends: Not estimatedThe source records don’t support an estimate.

Classification17 codes

H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10W 20/0698
Of conductive parts of the interconnections: local interconnections
H10B 41/27
With source and drain on different levels, e.g. with sloping channels: the channels comprising vertical portions, e.g. U-shaped channels
H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND