Method and IC design with non-linear power rails

A method for fabricating an integrated circuit (IC), comprising:

• receiving an IC layout having a first pattern layer and a second pattern layer to be formed on respective material layers of a semiconductor substrate, wherein
• the first pattern layer includes first conductive contact features and second conductive contact features spaced along a first direction, each of the first and second contact features having an elongated shape oriented in a second direction orthogonal to the first direction, and
• the second pattern layer includes a conductive via feature to be landing on the first the conductive contact features and to be distanced away from the second conductive contact features;
• and
• modifying the conductive via feature to a first polygon that is overlapped with the first conductive contact features and is distanced from the second conductive contact features, wherein the first polygon has an edge oriented in a tilted direction being different from the first and second directions, and wherein the conductive via feature is modified to have a S-curved shape.

A method for fabricating an integrated circuit (IC), comprising:

• receiving an IC layout having a first pattern layer and a second pattern layer to be formed on respective material layers of a semiconductor substrate, wherein
• the first pattern layer includes first conductive contact features and second conductive contact features spaced along a first direction, each of the first and second contact features having an elongated shape oriented in a second direction orthogonal to the first direction, and
• the second pattern layer includes a conductive via feature to be landing on the first the conductive contact features and to be distanced away from the second conductive contact features;
• and
• modifying the conductive via feature to a first polygon that is overlapped with the first conductive contact features and is distanced from the second conductive contact features, wherein the first polygon has an edge oriented in a tilted direction being different from the first and second directions, wherein the modifying of the conductive via feature includes
• abstracting a second polygon from the conductive via feature if a lateral distance between one of the second conductive contact features and the conductive via feature is less than a spacing target;
• and
• adding a third polygon to the conductive via feature if an overlapping area between one of the first conductive contact features and the conductive via feature is less than an overlapping target.