Semiconductor structure and manufacturing method thereof

A semiconductor FinFET structure, comprising:

• a semiconductor fin;
• a first metal gate comprising sidewall spacers, a gate dielectric layer, and a conductive portion spanning between the sidewall spacers, wherein a total width at a bottom of the sidewall spacer at one side of the conductive portion is measured as a sidewall spacer width;
• a first interlayer dielectric (ILD) surrounding the first metal gate, positioning over the semiconductor fin;
• a second ILD over the first ILD, wherein a bottom surface of the second ILD is coplanar with a top surface of the sidewall spacer;
• and
• a first protection layer over the first metal gate, wherein the first protection layer comprises a tapered sidewall,
• wherein a total width at a bottom level of the first ILD under the conductive portion and the gate dielectric layer is measured as a conductive portion width, and a total width of the first protection layer is greater than a sum of the conductive portion width and two times sidewall spacer width;
• a conductive plug penetrating the first ILD and the second ILD, wherein a first portion of the conductive plug is below a coverage of a vertical projection area of the first protection layer, and is in direct contact with the sidewall spacer of the first metal gate.

A semiconductor structure, comprising:

• a semiconductor layer having a source/drain region;
• a first gate over the semiconductor layer, the first gate comprising first sidewall spacers, a gate dielectric layer, and a conductive portion spanning between the first sidewall spacers, a total width at a bottom of the first sidewall spacer at one side of the conductive portion is measured as a sidewall spacer width;
• a second gate adjacent to the first gate, the second gate comprising second sidewall spacers;
• a first interlayer dielectric (ILD) surrounding the first gate and the second gate, contacting the first sidewall spacers and the second sidewall spacers;
• a second ILD over the first ILD;
• a first protection layer, positioning on a top surface of the conductive portion and a top surface of the first sidewall spacer, the first protection layer comprising a tapered sidewall,
• wherein a total width at a bottom of the gate dielectric layer is measured as a conductive portion width, and a total width of the first protection layer is greater than a sum of the conductive portion width and two times sidewall spacer width;
• a second protection layer over the second gate, wherein an interface between the first ILD and the second ILD is coplanar with a top surface of the first sidewall spacers of the first gate;
• and
• a conductive plug, wherein a first portion of the conductive plug is below a coverage of a vertical projection area of the first protection layer, and is in direct contact with a sidewall of the first sidewall spacer.