Semiconductor structure with air gap and method sealing the air gap
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHung-Chang Sun, Akira Mineji, Ziwei Fang
Life of this patent
Estimating the term…
Abstract
The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.
Claims20
A method of fabricating a semiconductor structure, comprising:
- receiving a substrate having an active region and an isolation region;
- forming gate stacks on the substrate and extending from the active region to the isolation region;
- forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks;
- forming an interlevel dielectric (ILD) layer on the substrate;
- removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer;
- and
- thereafter performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.
A method of fabricating a semiconductor structure, comprising:
- receiving a substrate having a shallow trench isolation (STI) feature and an active region, a gate stack on the substrate, an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks, and an interlevel dielectric (ILD) layer on the substrate, wherein the gate stack extends from the active region onto the STI feature;
- removing a portion of the outer gate spacer on the STI feature, resulting in an air gap between the inner gate spacer and the ILD layer;
- and
- thereafter performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.
A semiconductor structure, comprising:
- a substrate having an active region and an isolation region;
- gate stacks on the substrate and extending from the active region to the isolation region;
- a gate spacer on sidewalls of the gate stacks;
- and
- an interlevel dielectric (ILD) layer on the substrate and defining an air gap between the ILD layer and the gate spacer, wherein the ILD layer includes a top portion laterally extends to the gate spacer and caps the air gap, wherein the air gap is within the isolation region and is not extended to the active region.
Dependencies are inferred from the claim text.